S1a

advance & analogy — a study fork that walks past the netlist's edge, toward the physics underneath.

advance & analogy —— 一個走出網表邊緣、朝底下物理前進的研究分支。

The golden engine (S1) proved a binary switch-level netlist can match real silicon on 141 + 147 hardware-verified tests. S1a asks the next question: what is the minimum necessary physics to model the residue the netlist cannot express — and can we fill the gap between switch level and circuit/device level, one principled mechanism at a time?

黃金引擎(S1)已證明:二值開關級網表能在 141 + 147 顆硬體驗證測試上追平真矽。S1a 問下一個問題:要描述網表表達不了的那些殘餘,「最小必要的物理」是什麼 —— 我們能不能用一個個有原理的機制,把 switch-level 與 circuit/device-level 之間的縫填起來?

← Back to AprVisual← 回 AprVisual 主站 View on GitHub前往 GitHub S1a CLI referenceS1a 參數手冊

Fork scaffolded 2026-07-17 · starts life as a bit-exact clone of S1 (golden checksum verified) · study in progress分支建立於 2026-07-17 · 以 S1 的 bit-exact 克隆起跑(金 checksum 驗證)· 研究進行中

What this is這是什麼A study, not a product一場 study,不是一個產品

S1a is research-natured: an extended implementation that deliberately probes and challenges the physical and analog boundary of the netlist abstraction. The name's a carries a double meaning — advance, because it moves past where the golden engine stops; and analogy, in both senses of the word 類比: the electronic one (analog signals, charge, delay, drive strength) and the methodological one (modelling by physical analogy instead of by per-case patching).

S1a 是研究性質的:一個刻意去探測、挑戰網表抽象之物理與類比邊界的延伸實作。名字裡的 a 是雙關 —— advance(進階),因為它走過黃金引擎停下的地方;以及 analogy(類比),取「類比」一詞的兩面:電子的那面(analog:訊號、電荷、延遲、驅動強度),和方法的那面(用物理類推建模,而不是逐案打補丁)。

The division of labour is strict. S1 remains the untouched golden engine — fastest, bit-exact, the reference every experiment is measured against. S1a is a full fork (src/AprVisual.S1A/) that trades speed for principled physics, on purpose. Every mechanism lands behind its own switch, and every step is validated against three anchors: the golden checksum, the 141-test AccuracyCoin suite, and the 147-ROM regression.

分工是嚴格的。S1 保持不動,仍是黃金引擎 —— 最快、bit-exact、所有實驗的參考基準。S1a 是完整分支(src/AprVisual.S1A/),刻意用速度換有原理的物理。每個機制都躲在自己的開關後面,每一步都對三個錨驗證:金 checksum、141 顆 AccuracyCoin、147 顆回歸。

Why it exists為什麼存在The gap in the abstraction ladder抽象階梯上的那道縫

Simulation lives on a ladder. Each rung knows more physics and pays more compute. The strange thing about the rung we live on — the switch-level netlist — is how empty the space below it is: between "transistors as on/off switches" and "transistors as differential equations" there is a factor-of-millions cost cliff, and almost nobody builds there.

模擬活在一座階梯上。每一階懂得更多物理、付出更多計算。我們住的這一階 —— 開關級網表 —— 奇怪的地方在於它下面有多:從「電晶體是開關」到「電晶體是微分方程」之間,是數百萬倍的成本斷崖,而幾乎沒有人在那個空間裡蓋東西。

S1a's thesis: that gap is not empty because it is useless — it is empty because nobody had both a fast switch-level engine and a hardware-verified measuring stick to build it against. We now have both.

S1a 的命題:那道縫不是因為沒用才空著 —— 是因為從來沒有人同時擁有一個快速的開關級引擎一把硬體驗證的量尺,可以邊蓋邊對答案。現在我們兩樣都有了。

What we measured量到了什麼The campaign evidence: the gap has a shape戰役證據:那道縫有形狀

Two accuracy campaigns (288 hardware-verified tests) mapped the boundary empirically. The findings that define S1a's work list:

兩場精度戰役(288 顆硬體驗證測試)把邊界實測了出來。定義 S1a 工作清單的發現:

The plan計畫Seven mechanisms and a detection pass七個機制與一輪偵測

Mechanism機制Physics it restores還原的物理
M1Conductance-weighted resolution電導加權群解析ratioed drive fights (W/L)比例式驅動對抗(W/L)
M2Charge storage & decay電荷儲存與衰減bus hold, dynamic cells, on-die open-bus latch decay (not the board last-byte — that's M5e)匯流排保持、動態 cell、晶粒內 open-bus latch 衰減(不是板級 last-byte —— 那是 M5e)
M3RC propagation delayRC 傳播延遲cross-chip & long-line latency (timing-annotated netlist + geometry priors)跨晶片與長線延遲(時序標註網表 + 幾何先驗)
M4Sub-cycle transparent latches亞週期透明閂鎖closing-edge races, feedback loops關門沿賽跑、回授迴圈
M5Board-level component library板級元件庫TTL/CMOS parts around the dies晶粒周圍的 TTL/CMOS 零件
M5eBoard parasitic bus-hold板級寄生匯流排保持the capacitor nobody placed: open-bus last-byte on the external data bus (chartered 2026-07-18, design TBD)沒有人放的電容:外部資料匯流排的 open-bus last-byte(2026-07-18 立案,設計待議)
M6Power-on state & phase上電狀態與相位the boot lottery, CPU/PPU alignment開機抽籤、CPU/PPU 對齊
M7Canonical renumbering正準重編號determinism under graph changes圖變更下的決定論

Before any mechanism: Phase 0, the detection pass — six programmable structural scanners (latch races, cross-chip samplers, mid-flight aborts, feedback loops, geometry ranking, glitch capture) that enumerate where the physics matters, so mechanisms are built for measured targets, not guesses. The goal metric is not "zero shims" — it is zero hand-written special cases.

任何機制之前:Phase 0,偵測 pass —— 六個可程式化的結構掃描器(閂鎖賽跑、跨晶片取樣、中途廢止、回授迴圈、幾何排名、毛刺捕捉),先列舉物理在哪裡要緊,讓機制為量測過的目標而蓋、不是為猜測而蓋。目標指標不是「零 shim」—— 是零手寫特例

The toolbox解析工具箱One Python per mechanism, one article per Python一個機制一隻 Python,一隻 Python 一篇專文

Each mechanism M1–M7 gets an analysis program (in s1a/py/, stdlib-only, bring-your-own netlist files): it either detects structure in the netlist or computes physical reference parameters from transdefs/segdefs geometry. Each program is paired with a standalone deep-dive article — principles first, SVG figures from real runs, and an explicit account of which shims the mechanism will let us retire.

M1–M7 每個機制配一隻解析程式(放在 s1a/py/,只用標準函式庫、自備網表檔):它要嘛偵測網表結構,要嘛從 transdefs/segdefs 幾何算出物理參考參數。每隻程式配一篇獨立深入專文 —— 先講原理,配真實跑出來的 SVG 圖,並明說這個機制將讓哪些 shim 退役

Netlist provenance — the figures use the CORRECTED netlist. All figures and JSON here are computed on the curated data/system-def/ netlist, not the raw upstream Visual6502 dump. The raw 2A03 extraction dropped two real pull-down transistors (the R4015 read-decode a1 term restored as t13032b, and an ACLK-phase device t14634b) — devices whose geometry is present in segdefs but that the extraction missed. The un-patched netlist is therefore inherently distorted: analysing it would mis-model the APU register-read decode. The corrected 2A03 carries 10,918 devices (raw: 10,916); the 2C02 needed no patch (a geometry audit found zero misses). The aggregate statistics barely move, but the analyses stand on the netlist the engine actually simulates, not the flawed source. 網表出處 —— 圖用的是「修正版」網表。這裡所有圖與 JSON 都是用整理過的 data/system-def/ 網表算的,不是上游 Visual6502 的原始傾印。原始 2A03 抽取漏掉了兩顆真實的下拉管(R4015 讀取解碼的 a1 項,以 t13032b 補回;以及一顆 ACLK 相位器件 t14634b)—— 這些器件的幾何在 segdefs 裡明明存在,只是抽取時漏了。所以未修正的網表本來就是失真的:拿它分析會把 APU 暫存器讀取解碼模型錯。修正版 2A03 有 10,918 顆器件(原始:10,916);2C02 不需補丁(幾何稽核零漏)。aggregate 統計幾乎不動,但分析站在引擎真正模擬的網表上,不是有瑕疵的來源上。

Staged, always verified. This is deliberately long-running work, not a big bang. The ritual per package: analysis script → article → (on the user's go) S1A engine mechanism → retire the shim → full gates every single time: golden checksum with the mechanism off, AC 141/141 + the 147-ROM regression with it on. A shim removed without verification didn't happen. Working ledger: MD/S1a/02_解析工具箱_網站專文_shim退役_長期TODOLIST.md.

分段走,步步驗證。這是刻意的長線工作,不是大爆炸。每組工作包的節奏:解析程式 → 專文 →(使用者發令後)S1A 引擎機制 → 拔 shim → 每一次都過完整驗證閘:機制關 = 金 checksum 不變;機制開 = AC 141/141 + 147 回歸不退步。拔了 shim 沒驗證 = 沒發生。工作總帳:MD/S1a/02_解析工具箱_網站專文_shim退役_長期TODOLIST.md

PythonArticle專文Detects / computes偵測 / 計算Shims targeted瞄準的 shimShim retired @shim 拔除 commitStatus狀態
M2m2_charge_wins.pyWho wins when nothing is driving?電容誰輸誰贏? per-node physical capacitance from die polygons + gate W×L; re-runs every floating-pair election vs the engine's connection-count proxy — 10.3% flip, 12.5% are walk-order lotteries (9,682 pairs, both dies)從晶粒多邊形 + 閘極 W×L 算每節點物理電容;把每場浮接對選舉對引擎連接數代理重投 —— 10.3% 翻盤、12.5% 是走訪順序抽籤(兩晶粒 9,682 對) io_db decay · OpenBus → M5e* · OamBlankEdge · DL689c8fd
io_db decay retired (timestamp-decay mechanism)io_db 衰減退役(時戳衰減機制)
1 retired退役 1
M1m1_device_census.pyThe die's strength vocabulary晶粒的強度詞彙 transdefs W/L for all 27,788 devices → device classes + a 19/16-class half-octave strength lattice (top-8 > 93%); the 4:1 audit derives the missing depletion-load strength (S ≈ 0.58/0.95); 538 driver-vs-driver fight sites, 194 within 2× — incl. io_db, ale, the db/ab pads27,788 顆器件的 transdefs W/L → 器件分類 + 19/16 級半八度強度格(前 8 級 > 93%);4:1 稽核反推遺失的負載強度(S ≈ 0.58/0.95);538 個驅動對驅動打架點、194 個在 2× 內 —— 含 io_db、ale、db/ab pad LxaMagic · AluLatchlive
M3m3_elmore_binner.pyEvery net gets a clock每張網都有自己的時鐘 per-net Elmore τ composed from the first two studies (R from M1's W/L, C from M2's areas): 11,343 nets binned, ~5% delay-island candidates; slowest nets = the CPU↔PPU interface + clock trees + pads; median rise/fall 6.4×/3.9× (textbook 4:1); only 0.45% of nets can do dot-339's 16/18 — follow-up tool m3_inversion_parity.py tested the parity explanation: inconclusive (shortest-path parity is endpoint-dependent, 1 odd / 3 even) — an honestly-open anomaly用前兩份普查組成 per-net Elmore τ(R 來自 M1 的 W/L、C 來自 M2 的面積):11,343 張網分級,~5% 延遲島候選;最慢網 = CPU↔PPU 介面 + 時鐘樹 + pad;中位 rise/fall 6.4×/3.9×(教科書 4:1);只有 0.45% 的網做得到 dot-339 的 16/18 —— 後續工具 m3_inversion_parity.py 測了奇偶解釋:無結論(最短路徑奇偶對端點敏感,1 奇/3 偶)—— 誠實保持開放的異常 the four delay shims' constants四顆延遲 shim 的常數live
M4m4_latch_scan.pyEvery latch on two dies兩顆晶粒上的每一個閂鎖 pure topology, zero priors: 11,379 latch structures (2,494 pure cells + 8,129 gated + 2,348 cross-coupled incl. the 2,114 no-pull-up OAM cells, found structurally); 1,473 tight closing-edge races; self-validated — 8/11 campaign sites re-found, misses explained純拓撲零先驗:11,379 個閂鎖結構(純 cell 2,494 + 帶驅動 8,129 + 交叉耦合 2,348,含被結構自己點名的 2,114 個無上拉 OAM cell);1,473 場緊湊關門賽跑;自我驗證 —— 戰役站點 11 找回 8,漏抓有解釋 DL · DmcLatch · Dmc4015Abort · FrameIrq · Dbl2007 · OamDmaPpuBus + the transient half of+ 瞬態半邊的 OamBlankEdge689c8fd
DmcLatch + AluLatch proven (edge-latch primitive, now 3 verdicts: data-wins / hold / transparent); default-flip pending broad regressionDmcLatch + AluLatch 證明可退(edge-latch 原語,現 3 判決:data-wins / hold / transparent);預設翻轉待廣回歸
2 proven證明 2
M5m5_board_inventory.pyThe board as a circuit把主機板當電路 the system as 13 modules, 82 connections: boundary census (die↔die = 4 buses = the whole CPU/PPU interface), part inventory (74LS373 = 82 tr — the ALERead boss, real switch-level), and the structurally-undrivable controller auto-flagged (nes-pad's 4021/pslatch reverse-driven chain)系統 = 13 模組、82 連線:邊界普查(晶粒↔晶粒 = 4 條匯流排 = 整個 CPU/PPU 介面)、零件清單(74LS373 = 82 tr,ALERead 魔王、真開關級)、結構性不可驅動手把自動標記(nes-pad 的 4021/pslatch 反驅鏈) BoardOctalLatch · behavioural joypad行為層手把 · M5e: OpenBus last-byte (chartered)M5e:OpenBus last-byte(立案)live
M6m6_interface_census.pyWhere phase can hurt相位會咬人的地方 P2 scan: 173 interface nodes → BFS → 203 counter-comparators → 66 phase-sensitive interfaces; the four M6 bosses re-found by pure structure. Engine mechanism landed (M6×M3, env M6X): one (trigger, gate, delay, window) table replaces the dot-339 + BGSerialIn + even_odd clamp shims — 8-arm bit-safe, retirement undecidable in isolation (in-suite verification queued)P2 掃描:173 介面節點 → BFS → 203 計數器比較器 → 66 個相位敏感介面;四個 M6 魔王純結構重找。引擎機制已落地(M6×M3,env M6X):一張 (trigger, gate, delay, window) 表取代 dot-339 + BGSerialIn + even_odd 三顆 clamp shim —— 8 臂 bit-safe,退役孤立不可判(套內驗證排隊中) dot-339 · BGSerialIn · even_odd (M6×M3) + reset-hold · power_up_palette (phase selector, unbuilt)dot-339 · BGSerialIn · even_odd(M6×M3)+ reset-hold · power_up_palette(相位選擇器,未建)live
M7m7_canonical_key.pyEnding the lottery終結抽籤 canonical key (class, layeredArea, structHash, degree); resolves 18% of ties on the PPU, 52% on the CPU, unifies the big replicated cell arrays (OAM/palette); finds name-symmetry ≠ structural symmetry (db bits are context-wired)正準鍵 (class, layeredArea, structHash, degree);解掉 PPU 18% / CPU 52% 平手,統一大型複製 cell 陣列(OAM/palette);發現名稱對稱 ≠ 結構對稱(db 位元 context-wired) (D-class lottery root)(D 類樂透根源)live

The "shim retired @" column is this ledger's proof-of-work. It stays "—" until the corresponding S1A mechanism has landed and the shim is actually removed; only then does it record the commit — and a commit only qualifies after passing the full gates: golden checksum unchanged with the mechanism off, AC 141/141 + the 147-ROM regression not regressing with it on.「shim 拔除 commit」欄是這本帳的存證欄。在對應的 S1A 機制落地、shim 真正拔掉之前,一律是「—」;拔掉後才記下那個 commit —— 而且 commit 要先過完整驗證閘才算數:機制關 = 金 checksum 不變;機制開 = AC 141/141 + 147 顆回歸不退步。

*One reclassification — OpenBus. It was first planned here under M2 (charge storage & decay). The retirement experiments overturned that: the open-bus last byte is held by the parasitic capacitance of the board's data bus — a node on neither die, absent from our segdefs geometry — so M2 charge arbitration (control FAIL 1) and the full M4 latch stack (control FAIL 1) both proved unable to reach it. It is reclassified to M5e, the board-level bus-hold charter, and stands as the shim ledger's one documented ceiling. The whole load-bearing behaviour is the last-byte replay: no on-die mechanism — not M2 charge, not the full M4 latch stack, not M3 delay — retires any part of it, so OpenBus appears under none of them, only M5e. *一次改判 —— OpenBus。它原本規劃在 M2(電荷儲存與衰減)底下。試拔實驗推翻了:open-bus 的 last byte 由主機板資料匯流排的寄生電容保持 —— 一個不在任何一顆晶粒上、我們 segdefs 幾何裡根本沒有的節點 —— 所以 M2 電荷裁決(對照 FAIL 1)與 M4 閂鎖全 stack(對照 FAIL 1)都證明碰不到它。它被改判到 M5e(板級 bus-hold 立案),並成為 shim 總帳裡唯一記錄在案的天花板。它承重的行為整個就是 last-byte 重播:沒有任何晶粒內機制 —— M2 電荷、M4 閂鎖全 stack、M3 延遲都不行 —— 能退役它的任何一部分,所以 OpenBus 出現在它們任何一個底下,只在 M5e。

On the die在晶粒上The Mx structures, lit up on the real siliconMx 結構,點亮在真實矽上

Every toolbox census above is a number — 2,114 OAM cells, 538 fight sites, 66 phase interfaces. This is where those numbers become places. Each page renders the real 2A03/2C02 layout (the segment polygons the switch-level engine simulates) live in your browser — drag to pan, wheel to zoom, hover any cell — and highlights the nodes that mechanism's detector flags, by category. One shared viewer (adapted from Visual6502's renderer); each page differs only in which detector's output it overlays.

上面每一份工具箱普查都是一個數字 —— 2,114 個 OAM cell、538 個打架點、66 個相位介面。這裡就是那些數字變成位置的地方。每頁把真實的 2A03/2C02 佈局(開關級引擎模擬的 segment 多邊形)在你瀏覽器裡即時渲染 —— 拖曳平移、滾輪縮放、停在任一 cell 上 —— 並依類別標出該機制偵測器點名的節點。一個共用檢視器(改編自 Visual6502 的渲染器);每頁只差在疊哪個偵測器的輸出。

Structural patterns — discrete graph structures結構性 pattern —— 離散圖結構

Physical heatmaps — shaded by a continuous quantity (background layers start off)物理熱度圖 —— 用連續物理量著色(背景層預設關)

Layout data is derived from the Visual 2A03/2C02 netlist (CC-BY-NC-SA); generated by WebSite/s1a/layout/gen_layout.py, detectors by the toolbox scripts' --dump-nodes.佈局資料衍生自 Visual 2A03/2C02 網表(CC-BY-NC-SA);由 WebSite/s1a/layout/gen_layout.py 生成,偵測器來自工具箱腳本的 --dump-nodes

The shim ledgershim 總帳Every patch, its purpose, and its honest fate每一個補丁,它的目的,以及它誠實的下場

A shim is a small, honest, test-mode override that supplies a behaviour the binary switch-level model structurally cannot express. The accuracy campaigns accumulated ~18 of them to reach 141/141 + 146/147. S1a's job is to replace each with a principled mechanism — but only where verification proves it. This ledger is the truth table: what each shim was for, and which of five fates it met. Where a mechanism fails to retire a shim, that is not hidden — it is recorded as a result, because a precisely-characterized ceiling is as valuable as a retirement.

shim 是一個小而誠實的測試模式覆蓋,補上二值開關級模型結構上表達不了的行為。精度戰役累積了約 18 個才達到 141/141 + 146/147。S1a 的工作是把每個換成有原理的機制 —— 但只在驗證證明得了的地方。這本總帳是真值表:每個 shim 為了什麼、以及它落到五種下場的哪一種。機制沒能退役某個 shim 的地方,不會被藏起來 —— 它被記成一個結果,因為一個精確刻畫的天花板,和一次退役一樣有價值。

Re-verified at K=1 (2026-07-19). The earlier verdicts were set during a window of tooling-configuration risk — the same conditions that briefly mis-scored the S1 baseline itself (an omitted ALEREAD_MUX env, and isolated control arms run at the wrong boot alignment K=0 instead of the campaign's K=1). So the foundation was re-certified first (AC 141/141 + 147 146/1 on the latest build), then every test-derived verdict below was re-run at K=1 on the rebuilt engine with each ROM's catalog flags applied (28 arms). The classifications held — headline correction: even_odd, UNDECIDABLE → PROVEN (its K=0 "hc-identical spectator" reading was a wrong-alignment artifact; at K=1 the control fails on 10-even_odd_timing and M6X replaces it), and OamDmaPpuBus's decidable control confirmed (FAIL). A follow-up discriminating-ROM hunt — finding a better isolated test, as even_odd's 10 was — then crossed two more: BGSerialIn → PROVEN (via AccuracyCoin_BGSerialInReal) and Dbl2007 → decidable (via double_2007_read, seconds vs the 2-h #67). The toolbox census numbers (M1–M7, deterministic on the corrected netlist) never needed re-checking. K=1 已重驗(2026-07-19)。先前的判決是在一段「工具參數有風險」的期間確立的 —— 正是後來連 S1 基礎本身都短暫算錯分的同一種條件(漏設 ALEREAD_MUX env;孤立對照臂跑在錯的開機對齊 K=0 而非戰役的 K=1)。所以先把基礎重新認證(最新 build 上 AC 141/141 + 147 146/1),再把下方每一個「test 跑出來的」判決用 K=1 在重建引擎上、帶每顆 ROM 的 catalog 旗標重跑(28 臂)。分類全數站得住 —— 頭條更正:even_odd,UNDECIDABLE → PROVEN(它 K=0 的「hc 逐位相同旁觀者」是錯對齊的假象;K=1 下對照在 10-even_odd_timing 失敗、M6X 取代得了),OamDmaPpuBus 的可判對照也確認(FAIL)。接著一輪鑑別 ROM 獵捕 —— 像 even_odd 的測試 10 那樣找更好的孤立測試 —— 又跨掉兩顆:BGSerialIn → PROVEN(靠 AccuracyCoin_BGSerialInReal)、Dbl2007 → 可判(靠 double_2007_read,秒級對比 #67 的 2h)。工具箱的普查數字(M1–M7,修正版網表上確定性算出)從頭到尾不需重驗。

RETIRED mechanism replaces it, three-arm verified (shim PASS / no-shim FAIL / mechanism PASS).機制取代,三段論證(shim PASS / 拔 shim FAIL / 機制 PASS)。

PROVEN mechanism proven able to replace it (three-arm passes); default-flip pending the broad 141/147 regression.機制已證明可取代(三段論過);預設翻轉待 141/147 廣回歸。

UNDECIDABLE the mechanism expresses it, but no isolated test discriminates (the control passes without the shim) — retirement needs in-suite evidence.機制能表達,但沒有孤立測試能鑑別(對照組拔 shim 也過)—— 退役需套內證據。

CEILING a structural boundary no on-die mechanism can reach; the shim stays, and the reason is documented.晶粒內機制碰不到的結構邊界;shim 留住,理由記錄在案。

ACTIVE still a shim; its mechanism is designed but not yet built or verified.仍是 shim;機制已設計但尚未實作或驗證。

Which of the seven mechanisms appear here. This ledger is indexed by shim, so a mechanism shows up only where it replaces a specific shim's behaviour — you'll see M1 (LXA), M2, M3, M4, M6, and M5's board-net extension M5e (OpenBus). Two toolbox mechanisms have no row by nature: M5 (the board component library) models parts already in the netlist — the 74LS373, the 4021 — rather than fixing a shim; and M7 (canonical renumbering) is a cross-cutting determinism fix for the D-class boot lottery, with no single shim to replace. Their absence is a property of the ledger's shim-indexing, not a gap.七個機制裡,哪些會出現在這裡。這本總帳按 shim 列,所以一個機制只有在它取代某顆 shim 的行為時才會出現 —— 你會看到 M1(LXA)、M2、M3、M4、M6,以及 M5 的板網延伸 M5e(OpenBus)。有兩個工具箱機制天生沒有列:M5(板級元件庫)是把網表裡本來就有的零件 —— 74LS373、4021 —— 建模出來,不是拿來修 shim;而 M7(正準重編號)是針對 D 類開機抽籤的全域決定論修法,沒有任何單一 shim 可對應。它們的缺席是「總帳按 shim 索引」的性質,不是漏洞。

ShimshimWhat problem it solves解決什麼問題Mechanism機制Fate下場
io_db decaythe PPU open-bus latch leaks to 0 in ~600 ms when unrefreshed; floating nodes hold foreverPPU open-bus latch 不刷新時 ~600ms 漏到 0;浮接節點永遠保持M2 timestamp decayRETIRED 689c8fd
in-suite 141 confirmation running套內 141 確認跑中
DmcLatchDMC pcm_latch closing-edge race — the data should win (7-dmc_basics #19 reads $80)DMC pcm_latch 關門沿賽跑 —— 資料應贏(7-dmc_basics #19 讀 $80)M4 edge · data-winsPROVEN
AluLatchALU input latch hold-time — the phi-boundary bus collapse must not leak into the latch (ANC/ALR/ARR)ALU 輸入閂鎖 hold-time —— φ 邊界匯流排崩塌不可漏進閂鎖(ANC/ALR/ARR)M4 edge · holdPROVEN
dot-339$2001 rendering-enable arrives 24 hc late; the hpos=339 sprite-reset comparator fires one comparison early (StaleSprite T3)$2001 渲染致能晚到 24hc;hpos=339 精靈重置比較器早一次比較開火(StaleSprite T3)M6×M3 · ClampGateUNDECIDABLE
BGSerialIn$2001-enable at the hpos%8 shifter-reload boundary is delayed 16 hc, so the reload is skipped$2001 致能在 hpos%8 移位器 reload 邊界延遲 16hc,reload 被跳過M6×M3 · ClampGatePROVEN
discriminating-ROM hunt (2026-07-19): undecidable on AccuracyCoin_BGSerialIn, but on the untried AccuracyCoin_BGSerialInReal the 3-arm is clean — base PASS / NO_BGS_SHIM control FAIL (0/1) / M6X mechanism PASS. A better isolated test crossed it undecidable → proven (like even_odd 09→10); default-flip pending broad regression.鑑別 ROM 獵捕(2026-07-19):在 AccuracyCoin_BGSerialIn 上不可判,但換到還沒試過的 AccuracyCoin_BGSerialInReal 三段論乾淨 —— base PASS / NO_BGS_SHIM 對照 FAIL(0/1) / M6X 機制 PASS。一顆更好的孤立測試把它從不可判帶到已證(如 even_odd 09→10);預設翻轉待廣回歸。
even_odd$2001 write effect is 16 hc late in the vpos261 / hpos338-339 pre-render skip window$2001 寫效果在 vpos261 / hpos338-339 預渲染 skip 窗晚 16hcM6×M3 · DelayTransitionPROVEN
re-verified K=1 (2026-07-19): on 10-even_odd_timing base PASS / no-delay control FAIL (#3 "clock skipped too late") / M6X mechanism PASS — decidable, and the mechanism replaces it. (09-even_odd_frames stays undecidable — its control passes.) The earlier "hc-identical spectator" reading was a K=0 wrong-alignment artifact; default-flip pending the broad regression.K=1 重驗(2026-07-19):在 10-even_odd_timing 上 base PASS / 拔延遲對照 FAIL(#3「clock skipped too late」) / M6X 機制 PASS —— 可判,而且機制取代得了它。(09-even_odd_frames 仍不可判 —— 對照組會過。)先前「hc 逐位相同旁觀者」是 K=0 錯對齊的假象;預設翻轉待廣回歸。
DLthe DL/idl input latch captured a mid-settle bus glitch at a $4016/$4017 read (should track the settled bus)DL/idl 輸入閂鎖在 $4016/$4017 讀取捕捉了 mid-settle 匯流排毛刺(應追隨 settled 匯流排)M4 · transparentUNDECIDABLE
OamBlankEdgea rendering-disable edge writes $FF into the no-pull-up OAM cells; hardware's inertia ignores the pulse關渲染邊沿把 $FF 寫進無上拉 OAM cell;硬體慣性忽略脈衝M4 · holdUNDECIDABLE
OpenBus (last byte)an open-bus read returns the last byte transferred on the pins, held by the external bus capacitanceopen-bus 讀取回傳接腳上最後傳輸的位元組,由外部匯流排電容保持M5e (chartered)(已立案)CEILING
for on-die mechanisms — M5e charters the board-net home對晶粒內機制而言 —— M5e 立案板網的家
LXA magicthe $AB magic constant is a ratioed analog bus fight (AC vs data latch) → $FF on this silicon$AB magic 常數是比例式類比匯流排對抗(AC vs 資料閂鎖)→ 這批矽上是 $FFM1 · strengthACTIVE
Dmc4015Aborta deferred $4015 disable aborts an in-flight DMC DMA (the kill signal travels a long internal path)延遲的 $4015 disable 中止進行中的 DMC DMA(kill 訊號走內部長路徑)P3 / M3 internalUNDECIDABLE
FrameIrqa settle-internal pulse caught by an RS pair (latch race)settle 內脈衝被 RS 對咬(閂鎖賽跑)M4 · P6ACTIVE
Dbl2007back-to-back $2007 reads inside the merge window collapse into one buffer advance合併窗內背靠背 $2007 雙讀塌成一次緩衝推進M4 · P1 · ClampBusPROVEN
the hunt found a fast decidable defender (double_2007_read, seconds vs #67's ~2 h), so the mechanism could be built + verified cheaply: the M4·P1 ClampBus mechanism (env M4_P1) replaces the shim — base PASS / control FAIL (CRC 85CFD627 → D84F6815) / mechanism PASS with hc bit-identical to the shim (9,946,280). Gate A golden unchanged; OamDmaPpuBus folds into the same M4·P1 mechanism as a QueuedDrive row; default-flip pending broad regression.獵捕找到快速可判防守者(double_2007_read,秒級對比 #67 的 ~2h),所以機制能便宜地建 + 驗:M4·P1 ClampBus 機制(env M4_P1)取代 shim —— base PASS / 對照 FAIL(CRC 85CFD627 → D84F6815)/ 機制 PASS,hc 與 shim 逐位相同(9,946,280)。Gate A 金不變;OamDmaPpuBus 折進同一個 M4·P1 機制當 QueuedDrive 列;預設翻轉待廣回歸。
OamDmaPpuBus$4014 DMA writes to $2004 must hold the PPU I/O-bus data through OAM /WE$4014 DMA 寫 $2004 時 PPU I/O 匯流排資料須 hold 過 OAM /WEM4 · P1 · QueuedDriveACTIVE
re-verified K=1: the #67 "DMA + PPU bus" control FAILs (#67) — decidable. Its mechanism is now built: the M4·P1 QueuedDrive row (env M4_P1, same env as Dbl2007's ClampBus) supersedes the shim, running at its own chain point so it reproduces the shim bit-for-bit. Gate A golden unchanged, arming confirmed; the definitive #67 three-arm is running — flips to PROVEN on its result.K=1 重驗:#67「DMA + PPU bus」對照失敗(#67) —— 可判。機制現在已建:M4·P1 QueuedDrive 列(env M4_P1,與 Dbl2007 的 ClampBus 同 env)取代 shim,在自己的鏈點跑、逐位重現 shim。Gate A 金不變、武裝已確認;權威 #67 三臂跑中 —— 結果一到就翻 PROVEN。
ALERead mux$2007 read access arrives one CPU cycle early vs the '373 latch capture window (a node-split phase mux, in-suite proven)$2007 讀取存取早一個 CPU cycle 於 '373 閂鎖捕捉窗(node-split 相位 mux,套內已證)M6 · node-splitACTIVE (own mechanism)(自有機制)
PpuAleReadFeedbacka CHR-ROM read feeding back through the ALE path can re-trigger itself inside one settle (a P4 feedback loop); the guard breaks the cycleCHR-ROM 讀取經 ALE 路徑回授,可在一個 settle 內重新觸發自己(P4 回授環);guard 打斷這個環P4 · M4 feedbackACTIVE
PowerUpState · reset-holdpower-on register / palette state and CPU/PPU divider phase (the boot lottery, 4 alignments)上電暫存器 / palette 初態與 CPU/PPU 除頻相位(開機抽籤,4 種對齊)M6 · phase selectorACTIVE
Why one shim is a permanent ceiling. OpenBus's last byte is not an on-die node at all — it is the charge held by the package and board bus capacitance between the pins. No mechanism that lives inside the two dies (charge arbitration M2, latch verdicts M4, delay M3) can reach it, and the experiment confirms it: the full M4 mechanism stack with the behavioral replay removed still fails, and M2 arbitration failed the same test earlier. This byte belongs to a board-level bus model (M5's territory / an L3 data layer). Keeping the shim here is not a defeat — it is the correct boundary between what the silicon graph knows and what only the board does. See the glitch-immunity study for the full experiment. 為什麼有一個 shim 是永久天花板。OpenBus 的 last byte 根本不是晶粒內的節點 —— 它是接腳之間封裝與主機板匯流排電容保持的電荷。任何活在兩顆晶粒內部的機制(電荷裁決 M2、閂鎖判決 M4、延遲 M3)都碰不到它,而實驗證實了:M4 全機制堆疊去掉行為重播仍失敗,M2 裁決也敗在同一測試。這個位元組屬於板級匯流排模型(M5 的地盤 / L3 資料層)。這裡留住 shim 不是失敗 —— 它是「矽電路圖知道的」與「只有主機板知道的」之間正確的邊界。完整實驗見毛刺免疫研究
Why some shims are "undecidable", not failures. DL, OamBlankEdge, and dot-339 each have a working mechanism (M4 transparent / M4 hold / M6×M3), and each is bit-safe — every mechanism-on run passes and the neighbours don't regress. But on every isolated ROM tried, the control (shim removed) also passes, because these shims defend scenarios that only arise mid-suite — so there is no test that fails without the shim, and the isolated protocol cannot judge them. Yet "undecidable" can be an artifact of testing the wrong ROM: even_odd already crossed to PROVEN at the K=1 re-check (its control FAILs on 10-even_odd_timing), and a discriminating-ROM hunt (2026-07-19) crossed two more — BGSerialIn to PROVEN (control FAIL on AccuracyCoin_BGSerialInReal, M6×M3 replaces it) and Dbl2007 to PROVEN (control fails on double_2007_read — seconds, vs the ~2 h #67 — and the M4·P1 ClampBus mechanism now replaces it hc-identical). The three named above survived that hunt: no candidate ROM discriminated them, so they genuinely need in-suite evidence over the full 141-test suite. Honest status beats a fabricated retirement. 為什麼有些 shim 是「不可判」而非失敗。DL、OamBlankEdge、dot-339 各自都有能動的機制(M4 transparent / M4 hold / M6×M3),而且都是 bit-safe —— 每個機制開的跑法都過、鄰居也不退步。但在試過的每一顆孤立 ROM,對照組(拔掉 shim)通過,因為這些 shim 防守的場景只在套內出現 —— 沒有會因拔 shim 而失敗的測試,孤立協定就判不了它們。然而「不可判」可能是測錯 ROM 的假象:even_odd 已在 K=1 重確認時跨到 PROVEN(它的對照在 10-even_odd_timing 會 FAIL),而一輪鑑別 ROM 獵捕(2026-07-19)又跨掉兩顆 —— BGSerialIn 到 PROVEN(對照在 AccuracyCoin_BGSerialInReal FAIL、M6×M3 取代)、Dbl2007 到 PROVEN(對照在 double_2007_read 上失敗 —— 秒級,對比 #67 的 ~2h —— 而 M4·P1 ClampBus 機制現在 hc 逐位相同地取代它)。上面點名的三顆撐過了獵捕:沒有候選 ROM 鑑別得了,所以它們是真的需要套內、跑滿 141 顆的證據。誠實的狀態勝過捏造的退役。

→ The full methodology, with the control-arm data re-verified at K=1 — including how even_odd crossed from "spectator" to decidable/PROVEN when the boot alignment was fixed: The decidability boundary — when can you retire a shim by testing it alone?→ 完整方法論,對照臂資料已在 K=1 下重驗 —— 含 even_odd 在修正開機對齊後如何從「旁觀者」跨進可判/PROVEN:可判定性的邊界 —— 什麼時候你能靠單獨測試退役一個 shim?

The other half另一半Built in public, taught as it goes公開地蓋,邊蓋邊教

S1a develops on two legs. One is engineering: the fork, the mechanisms, the regressions. The other is education: this site will accumulate technical and semi-academic articles that document the process honestly — the physics primers, the dead ends, the falsified hypotheses, the measurements with error bars. The campaign already showed the format works: a negative result rigorously written up (the last test) later produced its own refutation (breaking the ceiling) — and both articles stayed up, because the correction is the lesson.

S1a 用兩條腿走路。一條是工程:分支、機制、回歸。另一條是教育:這個站會累積技術與半學術性的專文,誠實記錄過程 —— 物理入門、死路、被證偽的假設、帶誤差棒的量測。戰役已經證明這個format行得通:一個嚴謹寫下的負面結果(《最後一顆》)後來生出了它自己的反駁(《打破天花板》)—— 而兩篇都留在站上,因為更正就是那堂課。

Planned write-ups (the working queue): the 16/18 rise-fall parity audit (a falsifiable prediction from the geometry consult); building the per-net Elmore binner and what the die's histogram looks like; auto-detecting every transparent latch on two dies; how a ratioed NMOS fight actually resolves; the board as a circuit; and a running lab-notebook series as each mechanism lands.

已排隊的專文(工作佇列):16/18 rise-fall 奇偶稽核(幾何諮詢給出的可證偽預言);打造 per-net Elmore 分級器、看看晶粒的直方圖長什麼樣;自動偵測兩顆晶粒上的每一個透明閂鎖;比例式 NMOS 對抗實際怎麼分勝負;把主機板當電路;以及每個機制落地時的實驗筆記系列。

Foundations考古文庫The investigations that created S1a催生 S1a 的那些調查

S1a was not designed on a whiteboard — it condensed out of casework. These five articles (on the main site) are the archaeology: each documents a real investigation that hit the netlist's boundary, and together they define the gap this fork studies.

S1a 不是在白板上設計出來的 —— 它是從一件件案子裡凝結出來的。這五篇(在主站上)就是考古紀錄:每篇都是一場撞上網表邊界的真實調查,合起來定義了這個分支要研究的那道縫。

Also essential context: the AccuracyCoin report (the thirteen-chapter war record, 141/141) and the 147-ROM report card — the measuring sticks every S1a mechanism must keep satisfying.

同樣是必要脈絡:AccuracyCoin 報告(十三章戰記,141/141)與 147 顆成績單 —— 每個 S1a 機制都必須持續滿足的量尺。

Where we are走到哪了Status & roadmap現況與路線

Design documents (Traditional Chinese) live in the repo: MD/S1a/00 (master plan, M1–M7) and MD/S1a/01 (timing-annotated netlist, detection patterns, geometry priors).設計文件(繁中)在 repo:MD/S1a/00(總綱,M1–M7)與 MD/S1a/01(時序標註網表、偵測 pattern、幾何先驗)。