The die knows its own delays晶粒知道自己的延遲

1 · A world with no time in it1 · 一個沒有時間的世界

A settle-to-quiescence engine answers one question per half-cycle: given these inputs, what does the network settle to? Signals do not travel; they simply are, everywhere at once, the moment the settle completes. That abstraction is what makes the engine fast — and it is also a systematic lie about physics. On the real die, every wire is a resistor, every gate is a small capacitor, and a signal crossing the chip is a bucket brigade of charge. Most of the time the lie is harmless: a 1982-era logic gate switches in 2–5 nanoseconds, and our engine's quantum — one half-cycle — is 23.3 ns. Whole cascades of logic settle comfortably inside a single tick.

settle-到-靜止的引擎每個半週期只回答一個問題:給這些輸入,網路會穩定到什麼狀態?信號不會「travel」;settle 完成的那一刻,它們就同時「存在」於所有地方。這個抽象讓引擎跑得快 —— 但它也是一個對物理的系統性謊言。真實晶粒上,每根線都是電阻、每個閘極都是小電容,一個橫越晶片的信號是一場電荷的水桶接力。多數時候這個謊言無害:1982 年的邏輯閘 2~5 奈秒就切換完,而我們引擎的量子 —— 一個半週期 —— 是 23.3 奈秒。一整串邏輯能舒舒服服地在單一個 tick 裡穩定下來。

But not always. The campaign that took AccuracyCoin from 115 to the doorstep of 141 kept colliding with the exceptions: effects that arrive late on silicon and instantly in our model. A $2001 write that reaches the PPU's rendering logic 2–5 dots after the CPU issued it. A $2007 read whose bus cadence ripple lands three dots downstream. An APU disable racing a DMA engine through a long internal control run. Each one cost a forensic campaign to measure, and each measurement became one hand-tuned constant in one surgical shim: 24 half-cycles here, 16 there, an asymmetric 16/18 pair somewhere else. Five anchors, bought at retail price.

但不是永遠。把 AccuracyCoin 從 115 帶到 141 門口的那場戰役,不斷撞上例外:在矽上遲到、在我們模型裡卻瞬間抵達的效應。一個 $2001 寫入,要在 CPU 發出後 2~5 dot 才觸及 PPU 的渲染邏輯。一個 $2007 讀取,它對匯流排節奏的漣漪落在三個 dot 之後。一個 APU 停用信號,和 DMA 引擎在一條長長的內部控制線上賽跑。每一個都花了一場取證戰役去量測,每個量測值都變成一個手工常數、放進一個外科手術式的 shim:這裡 24 個半週期、那裡 16 個、別處一對不對稱的 16/18。五個錨點,全是原價買來的。

2 · The physics was in the files all along2 · 物理一直都在檔案裡

Here is the thing we kept walking past. The Visual6502-style netlist has two files. transdefs lists every transistor — and with each one, its bounding box on the die, which is a proxy for its W/L ratio, which is its drive strength. segdefs lists every wire segment — as an actual polygon, with vertex coordinates and a layer number: metal, polysilicon, or diffusion. Our parser reads all of it and keeps only the connectivity; the geometry is discarded with a comment that says so. But area is capacitance. Length over width is resistance. Layer is material, and material sets the resistivity — polysilicon is several hundred times more resistive than metal. Everything a first-order timing model needs is sitting in the data we already load.

這就是我們一直路過卻沒撿的東西。Visual6502 系的網表有兩個檔案。transdefs 列出每一顆電晶體 —— 連同它在晶粒上的 bounding box,那是 W/L 比的代理,也就是驅動強度。segdefs 列出每一段線 —— 是真正的多邊形,帶頂點座標和一個層別編號:metal、多晶矽、或擴散區。我們的解析器全部讀進來,只留下連接性;幾何被丟棄,還附了一行註解說明。但面積就是電容。長除以寬就是電阻。層別就是材質,而材質決定電阻率 —— 多晶矽比金屬阻抗高好幾百倍。一階時序模型需要的一切,都躺在我們本來就會載入的資料裡。

3 · Thirty seconds of Elmore3 · 三十秒的 Elmore 課

The workhorse of pre-SPICE timing analysis is the Elmore delay: model the driver as a resistor, the wire as a chain of resistors, every gate and every square micron of wire as a capacitor, and sum R × C down the chain — each resistance multiplied by all the capacitance it must charge through itself. It is a bucket brigade, literally: the delay to fill the last bucket is the sum, over every pipe along the way, of that pipe's narrowness times all the water that has to pass through it. Elmore is famously wrong in the details — it ignores waveform shape, coupling, everything second-order — and famously right about which paths are slow and by roughly how much. That is the only question we need answered.

SPICE 之前的時序分析主力是 Elmore 延遲:把驅動端當電阻、線當一串電阻、每個閘極和每平方微米的線當電容,沿鏈把 R × C 加總 —— 每段電阻乘上所有必須經過它充電的電容。它就是字面上的水桶接力:填滿最後一個桶的時間,是沿路每根水管的「窄度」乘上「必須流過它的總水量」的總和。Elmore 出了名的在細節上不準 —— 它無視波形、耦合、一切二階效應 —— 也出了名的在「哪些路徑慢、大概慢多少」上很準。而那正是我們唯一需要回答的問題。

4 · The 1982 cookbook4 · 1982 年的食譜

The 2A03 and 2C02 are Ricoh NMOS parts from roughly 1982, a 4–6 µm process straight out of Mead & Conway's Introduction to VLSI Systems — the textbook that era's engineers actually used. Its rule-of-thumb parameters are exactly the fidelity our model deserves:

2A03 和 2C02 是 Ricoh 約 1982 年的 NMOS 晶片,4~6 µm 製程,正是 Mead & Conway《Introduction to VLSI Systems》—— 那個年代工程師真正在用的教科書 —— 的世界。它的經驗參數,恰好就是我們模型配得上的精度:

The recipe per net: capacitance = polygon area × the layer's fF/µm², plus fan-out (each driven transistor's bbox area × C_ox); wire resistance = sheet resistance × squares, with the polygon's bounding-box aspect ratio as a serviceable proxy for squares; driver resistance by type — a weak depletion pull-up rising, a strong enhancement pull-down falling. Sum the Elmore products. One Python pass over files we already parse.

每條網的配方:電容 = 多邊形面積 × 該層的 fF/µm²,加上扇出(每顆被驅動電晶體的 bbox 面積 × C_ox);線阻 = sheet 電阻 × squares,多邊形的 bounding-box 長寬比是夠用的 squares 代理;驅動電阻看類型 —— 上升靠弱 depletion 上拉、下降靠強 enhancement 下拉。把 Elmore 乘積加總。對我們本來就解析的檔案,跑一遍 Python 就完了。

5 · Why first-order is enough: the quantum saves us5 · 為什麼一階就夠:量子救了我們

Here is the pivotal arithmetic. One half-cycle is 23.3 ns. A lightly-loaded 1982 gate switches in 2–5 ns. So most of the chip lives below the engine's resolution — its delays round to zero half-cycles, which is exactly what the zero-delay engine already assumes, which is why 288 hardware-verified tests could pass with only a handful of shims. The nets that matter are the exceptions: heavily-loaded long lines, high fan-out control signals, chains of pass transistors, and the pads. Those reach tens of nanoseconds — one to a few half-cycles — and those are the ones Elmore's order-of-magnitude accuracy classifies reliably. The estimator is not a calculator; it is a binner:

關鍵的算術在這裡。一個半週期 23.3 奈秒。一個輕載的 1982 年邏輯閘 2~5 奈秒切換。所以晶片的大部分活在引擎的解析度以下 —— 它們的延遲四捨五入到零個半週期,恰好就是零延遲引擎本來的假設,也正是 288 顆硬體驗證測試只需要一小把 shim 就能通過的原因。要緊的是例外:重載長線、高扇出控制信號、pass 電晶體串聯鏈、以及 pad。那些會達到數十奈秒 —— 一到數個半週期 —— 而那些正是 Elmore 的數量級精度能可靠分類的對象。這個估算器不是計算機;它是一個分級器:

6 · Calibration: five anchors and one delicious surprise6 · 校準:五個錨點與一個美味的意外

A physical model with unknown scale plus a few exact measurements is a regression problem, and the campaign already paid for the measurements: the 24-half-cycle CPU→PPU interface delay, two independent 16-half-cycle boundaries ($2001's rendering-enable path and the background shifter-reload path), the DMC control run, and a 16/18 rise/fall pair. The discipline is to spend them correctly. The cross-chip anchor is quarantined: most of its 24 half-cycles live in the pads, the package and the board traces — physics the die polygons cannot see — so pad-crossing nets get it as an external constant. The intra-chip anchors then fit one global RC-to-half-cycle multiplier. And the rise/fall pair calibrates the asymmetry ratio between the weak pull-up and the strong pull-down.

一個尺度未知的物理模型,加上幾個精確量測,就是一道迴歸題,而戰役早已付清量測的帳:24 半週期的 CPU→PPU 介面延遲、兩個獨立的 16 半週期邊界($2001 的渲染致能路徑、背景 shifter 重載路徑)、DMC 控制線、以及一對 16/18 的 rise/fall。紀律在於把它們花在對的地方。跨晶片錨點要隔離:它的 24 個半週期大多住在 pad、封裝與板級走線裡 —— 晶粒多邊形看不見的物理 —— 所以跨 pad 的網把它掛成外部常數。晶片內錨點則擬合一個全域的「RC 對半週期」乘數。而那對 rise/fall 用來校準弱上拉與強下拉之間的不對稱比。

7 · Two traps that bite7 · 兩個會咬人的陷阱

Pass-gate chains grow as N². NMOS designers loved series pass-transistor logic — carry chains, shifters, multiplexer trees. A chain of N pass gates is a distributed RC line: its Elmore delay goes as N(N+1)/2, not N. Treat the chain as one lumped node and you will underestimate exactly the structures most likely to be slow. The graph walk must detect source-drain series chains and apply the quadratic form. Bootstrapped nodes lie in the other direction. To rescue pass-gate logic from threshold loss, the era's designers boot-strapped clock and enable drivers above V_dd with an isolation capacitor; those nodes drive far harder than their DC geometry suggests, and naive RC overestimates them. Both traps are structural — detectable from the netlist — and the fringe capacitances, via resistances and temperature effects that terrify real EDA can all be ignored at half-cycle granularity.

Pass-gate 鏈以 N² 成長。NMOS 設計師熱愛串聯 pass 電晶體邏輯 —— 進位鏈、shifter、多工樹。N 顆 pass gate 的串聯是一條分布式 RC 線:它的 Elmore 延遲照 N(N+1)/2 走,不是 N。把整條鏈當一個集總節點,你低估的恰好是最可能慢的那些結構。圖走訪必須偵測 source-drain 串聯鏈、套用平方式。Bootstrap 節點往另一個方向說謊。為了拯救 pass-gate 邏輯的閾值損失,那個年代的設計師用隔離電容把時脈與致能驅動端自舉到 V_dd 以上;那些節點的驅動力遠強於它們的直流幾何,天真的 RC 會高估它們。兩個陷阱都是結構性的 —— 從網表可偵測 —— 而讓真正 EDA 頭痛的 fringe 電容、via 電阻、溫度效應,在半週期粒度下全部可以無視。

8 · Berkeley, 1983 — and what we have that they didn't8 · 柏克萊,1983 —— 以及我們有而他們沒有的東西

None of this is new physics. It is a forty-year-old discipline: Ousterhout's Crystal and Jouppi's TV (Berkeley, 1983) read chip layouts, extracted crude RC, and ran exactly this kind of first-order analysis to find critical paths in NMOS designs — the founding tools of static timing analysis. What is new is the direction and the ground truth. They analyzed layouts to predict silicon that did not exist yet. We hold silicon that has existed for forty years, netlists traced from its die photographs, and — the part they could never have — hardware-verified test ROMs whose pass/fail bits are exact functional measurements of the real chip's timing. Their method, our archaeology, and a verdict oracle at the end. The Visual6502 lineage of simulators has, as far as we know, never closed this loop: everyone stops at zero-delay logic. The loop is sitting there, waiting.

這裡沒有任何新物理。這是一門四十歲的學科:Ousterhout 的 Crystal 與 Jouppi 的 TV(柏克萊,1983)讀晶片版圖、抽取粗略 RC、跑的正是這種一階分析,在 NMOS 設計裡找臨界路徑 —— 靜態時序分析的開山工具。新的是方向與 ground truth。他們分析版圖,是為了預測還不存在的矽。我們手上是已經存在四十年的矽、從晶粒照片描出來的網表,以及 —— 他們永遠不可能有的 —— 硬體驗證的測試 ROM,其 pass/fail 位元是對真晶片時序的精確功能量測。他們的方法、我們的考古、加上終點的判定神諭。就我們所知,Visual6502 系的模擬器從未把這個迴圈closed起來:所有人都停在零延遲邏輯。這個迴圈就擺在那裡,等著。

9 · The payoff: from whack-a-mole to a constraint field9 · 報酬:從打地鼠到約束場

The difference this makes is not one number — it is who does the calibrating. Today, every timing constant is bought with a forensic campaign, and each new test that samples the same physics at a new boundary starts the game again. With geometric priors, the flow inverts: a script emits a delay estimate for every net; a binner sorts them into the four slots; the result becomes the first draft of the timing sidecar the analog-aware fork is designed to consume; and the test suite's job changes from calibrate to verify. Ninety-odd percent of nets land in their slot automatically. The residue — the bootstrap nodes, the super-buffers, the places where the model and the tests disagree — is exactly the interesting ten percent, and now it comes pre-flagged, with a physical reason attached. A disagreement stops being a bug hunt and becomes a measurement with an error bar.

這件事改變的不是某一個數字 —— 是校準這件事由誰來做。今天,每個時序常數都是用一場取證戰役買來的,而每顆在新邊界取樣同一種物理的新測試,都會讓遊戲重新開始。有了幾何先驗,流程反轉:一支 script 替每條網吐出延遲估計;分級器把它們排進四個槽;結果成為類比感知分支設計來消化的時序 sidecar 的初稿;而測試套件的工作從校準變成驗證。九成幾的網自動入槽。殘餘 —— bootstrap 節點、super-buffer、模型與測試不合的地方 —— 恰好是有趣的那一成,而且現在它們自帶預先標記、附著物理理由。一次不合,不再是一場抓蟲,而是一筆帶著誤差棒的量測。

Series: the semantic ceiling · crossing the analog boundary · the last test · breaking the ceiling. Record: consult tools/knowledgebase/a_geometry_delay_20260717; design notes in MD/S1a/01 (the timing-annotated netlist). Further reading: J. Ousterhout, "Crystal: A Timing Analyzer for nMOS VLSI Circuits" and N. Jouppi, "TV: An nMOS Timing Analyzer" (both 1983); C. Mead & L. Conway, Introduction to VLSI Systems (1980); W. C. Elmore (1948).系列:語意天花板·跨越類比邊界·最後一顆·打破天花板。紀錄:諮詢 tools/knowledgebase/a_geometry_delay_20260717;設計筆記在 MD/S1a/01(時序標註網表)。延伸閱讀:J. Ousterhout, "Crystal: A Timing Analyzer for nMOS VLSI Circuits" 與 N. Jouppi, "TV: An nMOS Timing Analyzer"(皆 1983);C. Mead & L. Conway,Introduction to VLSI Systems(1980);W. C. Elmore(1948)。