M5 · the board as a circuitM5 · 把主機板當電路
The interface is four buses介面就是四條匯流排
M5 is a board-level mechanism — it inventories the 7400-series glue between the two dies, not structures inside them. But its headline finding is visible on the die: the entire conversation between the NES's two most complex chips crosses just four die-die buses (~13 signals). Highlighted in red here on the 2C02 are exactly those — io_db[7:0], io_ab[2:0], io_rw, int — the whole CPU↔PPU interface. A separate, larger bus (blue) faces the board's VRAM; the control lines (orange) are what the 74LS373 latch and address decoders gate. Drag to pan, wheel to zoom, hover any node.
M5 是板級機制 —— 它盤點兩顆晶粒之間的 7400 系列膠合邏輯,不是晶粒內的結構。但它的頭條發現看得到在晶粒上:NES 兩顆最複雜晶片之間的全部對話,只跨過四條晶粒間匯流排(約 13 條訊號)。這裡在 2C02 上以紅色標出的正是它們 —— io_db[7:0]、io_ab[2:0]、io_rw、int —— 整個 CPU↔PPU 介面。另一條較大的匯流排(藍色)面向主機板的 VRAM;控制線(橘色)則是 74LS373 閂鎖與位址解碼器所閘控的。拖曳平移、滾輪縮放、停在任一節點上。
Faint background = the 2C02's layers. Bright fills = the interface signals M5's board census identifies. Board parts (the '373, decoders, controllers) live off-die and aren't drawn here — see the M5 study for the board map.暗色背景 = 2C02 各層。亮色填充 = M5 板級普查點名的介面訊號。板上零件('373、解碼器、手把)在晶粒外、這裡不畫 —— 板圖見 M5 專文。
How the detection works偵測演算法怎麼運作
M5's board census reads the whole system definition (nes-001 + cart), enumerates every module and connection, and classifies each connection by the boundary it crosses. The die↔die class comes out at just four buses — and every cross-chip timing boss the campaigns fought (dot-339, even_odd, ALERead, BGSerialIn) lives on them. This page resolves those interface signal names to their 2C02 node ids and lights them up; the point is how small the interface is relative to the ~16,000-node die around it.
M5 板級普查讀整個系統定義(nes-001 + 卡帶),列舉每個模組與連線,並依「跨越哪個邊界」分類每條連線。晶粒↔晶粒那一類算出來只有四條匯流排 —— 而戰役打過的每個跨晶片時序魔王(dot-339、even_odd、ALERead、BGSerialIn)都住在上面。本頁把這些介面訊號名解析成 2C02 節點 id 並點亮;重點是這個介面相對於周圍那顆約 16,000 節點的晶粒有多小。
| Boundary邊界 | What crosses it跨越什麼 |
|---|---|
| die ↔ die (4)晶粒 ↔ 晶粒(4) | io_ab[2:0] (register select) · io_db[7:0] (data) · int (NMI) · io_rw — the whole CPU↔PPU interface, and the M3/M6 delay islandio_ab[2:0](暫存器選擇)· io_db[7:0](資料)· int(NMI)· io_rw —— 整個 CPU↔PPU 介面,也是 M3/M6 的延遲島 |
| die ↔ board晶粒 ↔ 板 | the PPU↔VRAM address/data bus + chip selects + the '373 latch pathPPU↔VRAM 位址/資料匯流排 + 晶片選擇 + '373 閂鎖路徑 |
| board ↔ board板 ↔ 板 | decoder → latch → RAM glue, the controller chains解碼器 → 閂鎖 → RAM 膠合、手把鏈 |
74LS373, the undrivable controller — are off-die; the M5 study maps them.
為什麼這是 M5 的晶粒視角。其他結構頁點亮成千上萬的晶粒內 cell;M5 的故事相反 —— 承載整個跨晶片對話的線有多少。正因介面這麼小,它上面 24hc 的延遲(M3)才能讓一整個測試家族失步(M6)。讓它運作的板上零件 —— 完整建模的 74LS373、不可驅動的手把 —— 在晶粒外;M5 專文畫了它們。
Full board inventory: M5 · The board as a circuit →完整板級盤點:M5 · 把主機板當電路 →
Live layout rendering adapted from Visual6502's wires.js (MIT). Layout data from the Visual 2C02 netlist (CC-BY-NC-SA). Interface resolution: WebSite/s1a/layout/gen_m5_interface.py.
即時佈局渲染改編自 Visual6502 的 wires.js(MIT)。佈局資料來自 Visual 2C02 網表(CC-BY-NC-SA)。介面解析:WebSite/s1a/layout/gen_m5_interface.py。