The capacitor nobody placed沒有人放的那顆電容

Mechanism charter M5e. One shim survived every on-die mechanism we built — because the physics it stands in for is not on either die. The open-bus "last byte" lives in the parasitic capacitance of the board's data bus: a capacitor that appears on no schematic, placed by no designer, made of traces and everyone's pins. This page records the issue, the proof, and the charter for its eventual mechanism — deliberately designed later, documented now.

機制立案 M5e。有一顆 shim 在我們建的每一個晶粒內機制面前都存活下來 —— 因為它代打的物理根本不在任何一顆晶粒上。open-bus 的「last byte」活在主機板資料匯流排的寄生電容裡:一顆不出現在任何電路圖上、沒有任何設計者放置、由走線和大家的接腳組成的電容。本頁記錄這個 issue、證明、以及它未來機制的立案 —— 刻意留待日後設計,現在先記錄。

M5e · board parasitic bus-hold chartered 2026-07-18 — design TBD2026-07-18 立案 —— 設計待議

The physics物理 A capacitor made of wires and pins由線和腳組成的電容

The NES CPU data bus (D0–D7) strings together the 2A03, the PRG ROM, the work RAM, and (buffered) the PPU. When the CPU reads an address nothing answers — the open bus — the value it gets is whatever charge remains on the copper: the last byte anyone drove. What holds that charge is the bus net's parasitic capacitance: PCB trace-to-plane capacitance plus the package pins, bond wires, and input gates of every chip hanging on the bus. Tens of picofarads in total; with leakage currents this small, the level survives for milliseconds and more — vastly longer than the microseconds between CPU cycles, so a following read always sees the last byte. No component on the schematic is "the open-bus capacitor". The board provides it for free, by existing.

NES 的 CPU 資料匯流排(D0–D7)串著 2A03、PRG ROM、工作 RAM 和(經緩衝的)PPU。當 CPU 讀一個沒人回應的位址 —— open bus —— 它拿到的值,就是銅線上殘留的電荷:最後被任何人驅動過的位元組。保持這團電荷的,是匯流排網的寄生電容:PCB 走線對地電容,加上掛在匯流排上每一顆晶片的封裝接腳、bond wire 與輸入閘極。合計幾十 pF;漏電流這麼小,電位能存活毫秒以上 —— 遠長於 CPU cycle 之間的微秒,所以緊接的讀取永遠看得到 last byte。電路圖上沒有任何零件叫「open-bus 電容」。主機板光是存在,就免費提供了它。

The proof證明 Why every on-die mechanism failed — experimentally為什麼每個晶粒內機制都失敗 —— 實驗為證

Our graph models the two dies' interiors exactly (segdefs polygons — the M2 census computes real capacitance for every on-die node) and the board as ideal wires with no geometry. The bus trace and everyone's pin capacitance exist between the dies, in a region our data simply does not describe. The retirement experiments confirmed the consequence three independent ways (full record):

我們的圖精確建模兩顆晶粒的內部(segdefs 多邊形 —— M2 普查能算出每個晶粒內節點的真電容),而主機板是沒有幾何的理想導線。匯流排走線與大家的接腳電容存在於晶粒之間,在我們的資料完全沒有描述的區域。試拔實驗用三條獨立路徑證實了後果(完整紀錄):

OpenBus last-byte (this page)OpenBus last-byte(本頁)io_db decay (retired ✅)io_db 衰減(已退役 ✅)
where the capacitance lives電容在哪the board (traces + pins)板上(走線+接腳寄生)on-die (2C02 io-bus latch)晶粒內(2C02 io-bus 閂鎖)
hold time保持多久milliseconds and up毫秒級以上~600 ms then leaks to 0後漏到 0
in our graph?在我們的圖裡嗎no geometry at all❌ 零幾何real nodes (ppu._io_db)✅ 真節點
fate命運ceiling → M5e chartered天花板 → M5e 立案M2 timestamp decayM2 時戳衰減

The two are easy to confuse — both are "charge remembers a byte". The difference is jurisdiction: one capacitor is drawn in segdefs, the other exists only in the physical world between the packages.兩者很容易搞混 —— 都是「電荷記住一個位元組」。差別在管轄權:一顆電容畫在 segdefs 裡,另一顆只存在於封裝之間的物理世界。

The charter立案 M5e — give the bus its physics, in the right homeM5e —— 把物理還給匯流排,放進對的家

The honest fix is not another on-die mechanism — it is admitting the board's bus is a physical component our system model should carry, exactly as the 74LS373 already is. M5e charters that: extend the M5 board-component library with a bus-hold semantic for external nets — a capacitance annotation on the board-level data bus that remembers the last driven value and supplies it when nothing drives. The shim's logic barely changes; its home and legitimacy do: from "test-mode patch" to "physically-justified board net model", the same philosophy that made the '373 a first-class citizen instead of a hack in a callback.

誠實的解法不是再做一個晶粒內機制 —— 而是承認主機板的匯流排是一個系統模型本來就該攜帶的物理元件,就像 74LS373 已經是的那樣。M5e 立的就是這個案:把 M5 板級元件庫延伸出外部網的 bus-hold 語意 —— 在板級資料匯流排上掛一個電容標註,記住最後被驅動的值、在沒人驅動時供出它。shim 的邏輯幾乎不變;改變的是它的家與正當性:從「測試模式補丁」變成「有物理依據的板網模型」—— 跟讓 '373 成為一級公民、而不是回呼裡的 hack,是同一個哲學。

Deliberately chartered, not built. The design is left open on purpose (recorded now, decided later). The open questions it must answer: 刻意只立案、不實作。設計刻意留白(現在記錄、日後決定)。它必須回答的開放問題: