M3 · delay islands on the dieM3 · 晶粒上的延遲島
Every net gets a colour每一張網都有顏色
This is the real 2C02 silicon layout — the same segment polygons the switch-level engine simulates — rendered live in your browser. Painted over it is M3's Elmore-delay heatmap: every one of the 7,246 driven nets coloured by how long it takes to switch, cool (fast) → hot (slow). The red islands — the slowest ~5% — are not scattered at random: they cluster on the CPU↔PPU interface, the clock trees, and the pads. That is where the 24-half-cycle cross-chip latency the accuracy campaigns kept measuring physically lives. Drag to pan, wheel to zoom, hover any cell for its name and delay bucket. 這是真實的 2C02 矽佈局 —— 開關級引擎模擬的同一批 segment 多邊形 —— 在你瀏覽器裡即時渲染。上面塗著 M3 的 Elmore 延遲熱圖:7,246 張受驅動網每一張都依「切換要花多久」著色,冷(快)→ 熱(慢)。那些紅色的島 —— 最慢的約 5% —— 不是隨機散落:它們聚在 CPU↔PPU 介面、時鐘樹、以及接腳上。戰役一再量到的 24 個半週期跨晶片延遲,物理上就住在那裡。拖曳平移、滾輪縮放、停在任一 cell 上看它的名字與延遲級別。
Faint background = the die's layers (diffusion / poly / metal). Coloured fills = each net's delay bucket, cool → hot; islands drawn on top. A driven net with no polygon isn't drawn — but here all 7,246 have silicon area, so the map is dense. τ is in gate units (the median driven net ≡ 1.0), and clock trees / super-buffers are known over-estimates.暗色背景 = 晶粒各層(擴散 / 多晶矽 / 金屬)。彩色填充 = 每張網的延遲級別,冷 → 熱;島畫在最上層。沒有多邊形的受驅動網不會畫 —— 但這裡 7,246 張每一張都有矽面積,所以圖是密的。τ 以 gate 單位呈報(受驅動網中位數 ≡ 1.0),時鐘樹 / super-buffer 是已知的高估案。
How the delay map is built延遲地圖怎麼算出來的
Unlike M4's latch scan — pure topology, zero physical priors — M3 is the toolbox's one physical mechanism. It reads the die's geometry and puts a clock on every net: a first-order Elmore delay. Nothing here is new physics; the formula just composes the first two studies — resistance from M1's device strengths, capacitance from M2's polygon areas. The heatmap above is that τ, bucketed. This is what m3_elmore_binner.py computes; the colours are its output projected onto the layout.
跟 M4 的閂鎖掃描不同 —— 那是純拓撲、零物理先驗 —— M3 是工具箱裡唯一的物理機制。它讀晶粒的幾何,給每張網一個時鐘:一階 Elmore 延遲。這裡沒有新物理;公式只是把前兩份研究組起來 —— 電阻來自 M1 的器件強度、電容來自 M2 的多邊形面積。上面的熱圖就是那個 τ,分好級。這就是 m3_elmore_binner.py 算的東西;顏色就是它的輸出投影到佈局上。
τ(net) ≈ ( R_driver + R_wire/2 ) × C_net ← reported in GATE UNITS (median net ≡ 1.0)
C_net = Σ polygon-area × layer-weight + Σ gate W×L ← M2 areas (study #2)
R_driver = 20 kΩ / S, S = W/L of the strongest pull-down ← M1 strengths (study #1)
R_wire = Σ sheet-R × squares (squares = rectangle-equivalent L/W per polygon)Then every net's τ is normalised (median driven net ≡ 1.0) and dropped into four buckets — the heatmap legend above, documented: 接著把每張網的 τ 正規化(受驅動網中位數 ≡ 1.0),丟進四個級別 —— 就是上面熱圖的圖例,列在這裡:
| Bucket級別 | τ (gate units)τ(gate 單位) | 2C02 nets2C02 網數 | What lives here住著什麼 |
|---|---|---|---|
| fast快 | < 0.5 | 383 | tiny local nets — switch effectively instantly (the cool floor of the gradient)微小的本地網 —— 幾乎瞬間切換(梯度的冷底) |
| ordinary普通 | 0.5 – 2 | 5,478 | the logic bulk — this is what "1.0" means邏輯主體 —— 「1.0」指的就是這批 |
| slow慢 | 2 – 8 | 1,023 | long or high-fanout nets — warming toward annotation-worthy長線或高扇出網 —— 熱到接近值得標註 |
| delay island延遲島 | > 8 | 362 (5.0%) | the interface, clock trees, pads — where cross-chip latency lives介面、時鐘樹、接腳 —— 跨晶片延遲住的地方 |
pclk0/pclk1 (the pixel clocks), then _rd, _io_ce, _io_rw_buf, _io_db0–2: the bus between the two chips. That is the 24-half-cycle cross-chip delay family — the same physics behind the ALERead, dot-339, even_odd and BGSerialIn shims — given a purely geometric background check. The islands aren't a model artefact: the silicon is genuinely slow there, and it is slow exactly where the timing shims already live.
分級器根本不知道什麼是「CPU↔PPU 介面」。它只拿到多邊形與器件尺寸、別無其他 —— 但它排出來最熱的網,恰好就是 pclk0/pclk1(像素時鐘),接著是 _rd、_io_ce、_io_rw_buf、_io_db0–2:兩顆晶片之間的匯流排。那正是 24 個半週期的跨晶片延遲家族 —— ALERead、dot-339、even_odd、BGSerialIn 這些 shim 背後的同一套物理 —— 拿到了一次純幾何的身家調查。延遲島不是模型的假影:矽在那裡就是真的慢,而它慢的地方,恰好就是計時 shim 已經住著的地方。
Full write-up — the formula, the five hardware anchors, and the impossible 16/18 rise/fall asymmetry: M3 · Every net gets a clock →完整專文 —— 公式、五個硬體錨點、以及不可能的 16/18 rise/fall 不對稱:M3 · 每張網都有自己的時鐘 →
Live layout rendering adapted from Visual6502's wires.js (Brian & Barry Silverman, MIT). Layout data derived from the Visual 2C02 netlist (CC-BY-NC-SA) — the corrected data/system-def/. Detection: WebSite/s1a/py/m3_elmore_binner.py --dump-nodes.
即時佈局渲染改編自 Visual6502 的 wires.js(Brian & Barry Silverman,MIT)。佈局資料衍生自 Visual 2C02 網表(CC-BY-NC-SA)—— 修正版 data/system-def/。偵測:WebSite/s1a/py/m3_elmore_binner.py --dump-nodes。