Do the mechanisms transfer?機制帶得走嗎?

The seven S1a mechanisms (M1–M7) restore the ~1.1% analog residue a binary switch-level model cannot express. Natural question: would they help another analog-digital NMOS chip, or are they the NES's own? The answer splits cleanly on two layers — the physics class is a closed, universal set (any faithful switch-level+analog simulator hits the same six), so the method ports; but the code is instantiated on NES nodes, so the sites must be re-found. And three roles stand apart: M7 is engine-level with zero chip binding, M5 models the board (not the die), and M6 needs a second chip to fire at all.

S1a 的七個機制(M1–M7)還原了二值開關級模型表達不了的那 ~1.1% 類比殘差。自然的問題:它們對別的類比-數位混合 NMOS 晶片有用嗎,還是 NES 專屬?答案在兩層上乾淨地一分為二 —— 物理類別是一個封閉、普世的集合(任何忠實的開關級+類比模擬器都撞到同一批),所以方法可移植;但 code 是實例化在 NES 的節點上,所以位置要重找。而三個角色自成一格:M7 是引擎級、零晶片綁定,M5 模的是板子(不是晶粒),M6 需要第二顆晶片才觸發。

M1–M7 generality通用度 class vs site類別 vs 位置 2026-07-22

The key distinction關鍵區分 Physics class vs implementation site物理類別 vs 實作位置

S1a's whole design principle is to replace ad-hoc shims with white-box mechanisms grown from physics. Each mechanism answers a universal physical question — "does a dynamic node's charge leak away?", "who wins when two drivers fight a bus?" — but it fires at a specific NES node (e.g. ppu._io_db0). Those are two different things:

S1a 的整個設計原則,是把臨時的 shim 換成「從物理長出來」的白箱機制。每個機制回答的是一個通用的物理問題 ——「動態節點的電荷會漏光嗎?」、「兩個 driver 搶匯流排時誰贏?」—— 但它啟動在 NES 的某個具體節點(例:ppu._io_db0)。這是兩件不同的事:

  • The physics question is the class — chip-independent. The same question exists on a Z80, a 6800, any NMOS die.
  • 物理問題是類別 —— 與晶片無關。同一個問題在 Z80、6800、任何 NMOS 晶粒上都存在。
  • The firing location is the site — found per chip (from die geometry, or reverse-engineered from a failing test). It is this chip's fingerprint.
  • 啟動位置是位置 —— 逐晶片辨識出來的(從 die 幾何,或從失敗測試回推)。它是這顆晶片的指紋。

So "does it transfer?" is not yes/no. It is: the class travels; the site does not. The rest of this article measures how much of each mechanism is class and how much is site.

所以「帶不帶得走?」不是 yes/no,而是:類別帶得走;位置帶不走。本文其餘部分,量化每個機制有多少是類別、多少是位置。

Why the classes are universal為什麼類別是通用的 A closed taxonomy of six phenomena六個現象的封閉分類

The detection pass sorts all ~25 "hot spots" across the 288 hardware tests into six programmable structural patterns — and claims the taxonomy is closed (no hot spot across 288 tests falls outside these six):

偵測 pass 把 288 顆硬體測試裡的 ~25 個「雷點」全部歸進六個可程式化的結構 pattern,並宣稱分類封閉(288 測沒有一個雷點落在這六類之外):

PatternPatternPhysical phenomenon物理現象Mechanism機制
P1 latch race閂鎖賽跑a pass-gate closes in the same half-cycle its input collapsespass-gate 關門沿與輸入崩塌同半週期M4
P2 cross-chip sampling跨晶片取樣one chip samples before another's signal has arrived一晶片在另一晶片訊號到達前就取樣M6
P3 mid-flight abort中途廢止a control signal cancels an in-progress action same cycle控制訊號同週期廢止一個進行中的動作M3 / M4
P4 feedback回授a binary feedback loop (ALE+read) that won't converge二值回授迴圈(ALE+read)M4
P5 geometry / RC幾何 / RCcapacitance/resistance propagation delay電容/電阻造成的傳播延遲M2 / M3
P6 glitch毛刺a mid-settle transient captured by a latchsettle 中途的暫態被閂鎖捕捉M4

A closed taxonomy is the proof of generality. These six are not "what the NES happens to have" — they are the complete set of analog phenomena a two-state quiescent-settle model cannot express. Any faithful switch-level simulator of any NMOS/mixed-signal die hits these six and no seventh. So the methodology — use these six classes to fill the ~1% analog residue — is universal.

「封閉分類」本身就是通用性的證據。這六類不是「NES 剛好有這些」,而是二值 quiescent-settle 模型表達不了的類比現象的完整集合。任何 NMOS/混合訊號晶粒的忠實開關級模擬,都只會撞到這六類、沒有第七類。所以方法論——拿這六類去補那 ~1% 類比殘差——是通用的。

Mechanism by mechanism逐機制解剖 M1–M5 analog · M6 phase · M7 determinismM1–M5 類比 · M6 相位 · M7 決定論

The full roster splits into three roles. For each: the physics, whether the class is universal, and how tightly the current code is bound to the NES.

完整編號分三個角色。每個標:物理、類別是否通用、現在的 code 綁 NES 有多緊。

M1 — strength / ratio強度 / 比例 · class general, site NES類別通用,位置綁 NES

When several drivers fight one bus, the winner is set by drive strength (∝ W/L) — not a binary "nobody yields", but an analog voltage divide. Universal to any ratioed logic. But the current implementation is the 6502's LXA/ANE $AB "magic constant" ratio fight — a 6502-specific undocumented opcode. Class ports (a strength LUT / MOSSIM-II strength classes); the site (which bus, which opcode) is re-found. Calibration: W/L from transdef geometry.

多個 driver 搶一條匯流排時,贏家由驅動強度(∝ W/L)決定 —— 不是二值「誰都不讓」,而是類比電壓分壓。任何 ratioed logic 通用。但現在的實作是 6502 的 LXA/ANE $AB「magic constant」比例戰 —— 一個 6502 特定的未定義 opcode。類別可帶(強度 LUT / MOSSIM-II 強度類別);位置(哪條匯流排、哪個 opcode)要重找。校準:transdefs 幾何的 W/L。

M2 — charge storage & decay電荷儲存與衰減 · most universal最普世

A dynamic node that isn't being driven leaks its charge away over time (back toward 0); a high-capacitance node holds longer. This is the most universal analog effect — every NMOS die with dynamic (unrefreshed) nodes has it. Fires today on the 2C02 io_db bus (8 nodes, ~600 ms threshold), but the mechanism (a capacitance island + a decay threshold) is fully generic and the sites are auto-findable from geometry (no pull, only pass-gate driven). Calibration: segdef polygon area → node-capacitance proxy.

動態節點沒被持續驅動時,電荷會隨時間漏光(回到 0);電容大的撐得久。這是最普世的類比效應 —— 任何有動態(非刷新)節點的 NMOS 晶粒都有。現在啟動在 2C02 的 io_db 匯流排(8 節點、~600ms 門檻),但機制(電容島 + 衰減門檻)完全通用,且位置可從幾何自動找(無 pull、只被 pass-gate 驅動)。校準:segdefs 多邊形面積 → 節點電容代理。

M3 — RC propagation delayRC 傳播延遲 · class general, don't chase RC類別通用,別真追 RC

A signal through an RC path takes time; across chips and long lines it shows. A zero-delay binary model samples too early. Universal to any system with real RC delay. Today folded into "M6×M3 unified cross-chip phase arbitration" ($2001 write delay, etc.). Hard-won caveat (IRSIM lesson): do not integrate continuous RC in the hot loop — that drags an event-driven engine down. M3 is a discretised delay window, not a continuous RC solve.

訊號經過 RC 路徑要時間;跨晶片、長線特別明顯。零延遲的二值模型取樣太早。任何有真 RC 延遲的系統通用。現在和 M6 合併成「M6×M3 統一跨晶片相位仲裁」($2001 寫延遲等)。硬教訓(IRSIM):別在熱路徑真的積分連續 RC —— 那會拖垮 event-driven 引擎。M3 是離散化的延遲窗,不是連續 RC 求解。

M4 — transparent latch / feedback透明閂鎖 / 回授 · biggest; class strong, sites NES最大宗;類別強通用,位置綁 NES

A dynamic latch is transparent in one clock phase (it tracks its input) and locks on the closing edge; if that edge races the input's collapse, "data wins" vs "hold old" is decided by analog overlap. This is the biggest family (6+ shims). Universal — every dynamic latch / pass-gate latch / binary feedback loop has it. Instances are all 2A03/2C02-specific: DMC pcm_latch (data-wins), the ALU input latch (hold), $2007 double-read ClampBus, OAM-DMA bus, $4016/$4017 DL transparency, PPU ALE/read feedback. Class ports strongly (latches are everywhere); which latches race must be found per chip.

動態閂鎖在某個時脈相位是透明的(跟著輸入變),關門沿才鎖住;若關門沿撞上輸入崩塌,「資料贏」還是「舊值 hold」由類比重疊決定。這是最大宗(6+ shim)。通用 —— 任何動態閂鎖 / pass-gate latch / 二值回授迴圈都有。實例都是 2A03/2C02 特定:DMC pcm_latch(資料贏)、ALU 輸入閂鎖(hold)、$2007 雙讀 ClampBus、OAM-DMA 匯流排、$4016/$4017 DL 透明、PPU ALE/read 回授。類別強通用(閂鎖到處都是);哪些閂鎖會賽跑要逐晶片找。

M5 — board-level component library板級元件庫 · system-scoped (off-die)系統級(晶片外)

M5 models the TTL glue outside the 2A03/2C02 dies — the mainboard/cartridge parts: the 74LS373 octal latch, the CD4021 controller shift register, board ties/pulls. Its flagship win is ALERead (boing2k7): the "pure switch-level ceiling of 140/141" was broken to 141/141 by the board's 74LS373 (transparent positive feedback + bus capacitance holding $FF). The design charter is blunt: M5 is "not a garnish — it is the key to breaking the pure switch-level ceiling." Generality: the concept is the most universal of all ("model the board, not just the chip" — every multi-chip system has glue logic a chip-only netlist drops). But its object is the system's board — a different chip means a different board. Strictly, "another chip netlist" gains nothing from M5 (M5 covers the die's surroundings). Common TTL (373/374/CD4021/decoders) is cross-system, so the component library partly reuses.

M5 模型化 2A03/2C02 晶粒之外的 TTL glue —— 主機板/卡帶上的元件:74LS373 八進位閂鎖、CD4021 手把移位暫存器、板卡 tie/pull。它的旗艦戰功是 ALERead(boing2k7):「純開關級天花板 140/141」靠板上 74LS373(透明正回授 + 匯流排電容持 $FF)破到 141/141。設計總綱定調得很直接:M5「不是錦上添花,是破純開關級天花板的關鍵」。通用度:概念最通用(「連板子一起模,不只模晶片」—— 任何多晶片系統都有被純晶片網表漏掉的 glue logic)。但它的對象是系統的板子 —— 換晶片是另一套板子。嚴格說,「別的晶片 netlist」不受益於 M5(M5 補的是晶粒外圍)。常用 TTL(373/374/CD4021/decoder)跨系統共用,所以元件庫部分可重用。

M6 — power-up state / phase arbitration上電初態 / 相位仲裁 · needs ≥2 chips需 ≥2 晶片

Two effects: (a) the power-up state (residual charge, register randomness); (b) cross-chip phase — a counter/comparator on one chip must not act until a control change from the other chip has arrived. Universal to any multi-chip system. Instances: even/odd frame skip, dot-339 render sampling, BG serial reload, the realistic power-up palette residue. Class ports (queue-layered delta-cycle, break-before-make); the sites are NES cross-chip points. Precondition: M6 needs ≥2 chips to fire — a bare single CPU (6502/6800/Z80) has no cross-chip phase and doesn't need M6.

兩個效應:(a)上電初態(殘留電荷、暫存器隨機態);(b)跨晶片相位 —— 一晶片的 counter/comparator 在另一晶片的控制變化到達前不能先動。任何多晶片系統通用。實例:even/odd 幀跳格、dot-339 渲染取樣、BG serial reload、真實開機調色盤殘留。類別可帶(佇列分層 delta-cycle、break-before-make);位置是 NES 跨晶片點。前提:M6 需要 ≥2 顆晶片才觸發 —— 裸單 CPU(6502/6800/Z80)沒有跨晶片相位,不需要 M6。

M7 — canonical renumbering / determinism正準重編號 / 決定論 · engine-level · zero chip binding引擎級 · 零晶片綁定

A load-time canonical renumber (by class, layered area, structure hash, degree) so identical "twin" nodes (u7/u8) share a fate and a graph change no longer re-rolls the global node-id "lottery". It fixes the engine's floating-node tiebreak (largest-capacitance-holds) and some open-bus races, which depend on node-id order. Split of labour: M6 = temporal arbitration (power-up + cross-half-cycle); M7 = spatial arbitration of simultaneous events in one settle wave (who resolves first). This is the "M7 canonical topological ID". Generality: the most universal — it binds to no chip at all. It is a property of the engine, not any die; any switch-level simulator whose floating tiebreak depends on order benefits. Verdict: lift and drop, zero change. See the M7 study.

載入期正準重編號(class、layered area、structure hash、degree),讓同構「孿生」節點(u7/u8)同命、圖一變更就不再重擲全域 node-id「樂透」。它修的是引擎的浮接節點 tie-break(電容最大者保留前值)和 open-bus 某些賽跑,那些依賴 node-id 順序。分工:M6 = 時間仲裁(上電 + 跨半週期);M7 = 空間仲裁(同一 settle 波裡同時事件誰先解)。這就是「M7 正準拓撲 ID」。通用度:最通用 —— 根本不綁任何晶片。它是引擎的性質,不是任何晶粒;任何浮接 tie-break 依賴順序的開關級模擬都受益。判定:直接帶走、零改動。見 M7 專文。

At a glance一覽 Generality of each mechanism各機制的通用度

Mech機制 Object layer對象層 Class universal?類別通用? NES bindingNES 綁定 Another chip netlist gains?別的晶片 netlist 受益?
M1 strength強度on-die晶粒內✓class yes, site re-found類別可、位置重找
M2 charge/decay電容/衰減on-die晶粒內✓ most universal✓ 最普世low低high高
M3 RC delayRC 延遲on-die / cross-chip晶粒/跨晶片✓ (don't chase RC)✓(勿追 RC)class yes, site re-found類別可、位置重找
M4 latch/feedback閂鎖/回授on-die晶粒內✓ biggest✓ 最大宗class strong, sites re-found類別強、位置重找
M5 board parts板級元件✓ concept✓ 概念system-specific系統特定covers surroundings; TTL lib partly reuses補外圍;TTL 庫部分共用
M6 cross-chip/power-up跨晶片/上電cross-die跨晶粒✓needs ≥2 chips to fire需 ≥2 晶片才觸發
M7 canonical / determinism正準/決定論the engine引擎本身✓zero零lift & drop直接帶走

The genuinely NES-only cases live inside the M4 family: DMC-DMA-abort (needs the APU DMC channel), OAM blank-edge (needs the 2C02's DRAM OAM), frame-IRQ (2A03 APU), $2007/$2001 PPU register timing. For another chip these subsystems don't exist — it's not "re-find the site", it's "no such problem". Rough split: about half the mechanisms are "universal class + low/mid binding" (M2, M3, M4 core, M6, M7 — method and most code port); the other half are "universal class but bound in practice to an NES subsystem or a specific opcode" (M1 LXA, M4's DMC/OAM/frame-IRQ/PPU, M5's board).

真正只有 NES 才有的藏在 M4 家族裡:DMC-DMA-abort(需 APU DMC 通道)、OAM blank-edge(需 2C02 的 DRAM OAM)、frame-IRQ(2A03 APU)、$2007/$2001 PPU 暫存器時序。換晶片時這些子系統根本不存在 —— 不是「重找位置」,是「無此問題」。粗估:約一半機制是「通用類別 + 低/中綁定」(M2、M3、M4 核心、M6、M7 —— 方法與多數 code 可轉);另一半是「通用類別但實務綁死 NES 子系統或特定 opcode」(M1 LXA、M4 的 DMC/OAM/frameIRQ/PPU、M5 板子)。

The proof佐證 Bare CPUs need zero mechanisms裸 CPU 不需要任何機制

The core engine runs unchanged on three standalone dies — the bare MOS 6502, Motorola 6800, and Zilog Z80 — driven by an infinite NOP sled, and is bit-exact across the instruction set. Those three use none of M1–M7, because:

引擎核心不改一行就能跑三顆獨立晶粒 —— 裸 MOS 6502、Motorola 6800、Zilog Z80 —— NOP 灌注,且跨 ISA bit-exact。那三顆完全沒用到任何 M1–M7,因為:

This is exactly the point: M1–M7 are not part of the engine — they are the NES's analog-residue patches. The core engine is general; the mechanisms belong to this system. A new chip inherits the general engine and re-earns its own residue set.

這正好反證機制的定位:M1–M7 不是「引擎的一部分」,而是「NES 這個具體系統的類比殘差補丁」。核心引擎是通用的;機制是這顆系統的。新晶片繼承通用引擎,再自己賺回它的殘差集合。

Porting to a new chip移植到新晶片 What travels, what must be redone什麼帶得走,什麼要重做

Travels (method layer)帶得走(方法層)

  • the binary quiescent-settle core engine;
  • 二值 quiescent-settle 核心引擎;
  • the six-pattern detection pass + the "texture decides the mechanism" table — to find the new chip's residue;
  • 六類偵測 pass +「質地決定機制」判定表 —— 用來辨識新晶片的殘差;
  • M2/M3's geometry→capacitance/RC proxies, M1's strength LUT, M4's latch-race detector framework, and M7 outright;
  • M2/M3 的幾何→電容/RC 代理、M1 的強度 LUT、M4 的閂鎖賽跑偵測框架,以及 M7 整個直接用;
  • M5's common-TTL component library (373/374/CD4021/decoder), partly.
  • M5 的常用 TTL 元件庫(373/374/CD4021/decoder),部分。

Redone (site layer)要重做(位置層)

  • run the new chip's tests → find its hot spots → sort into the six → instantiate on its nodes;
  • 跑新晶片的測試 → 找雷點 → 歸六類 → 在它的節點上實例化;
  • M6's cross-chip points, M1's ratio-fight opcode, M4's specific latches, M5's this system's board;
  • M6 的跨晶片點、M1 的比例戰 opcode、M4 的具體閂鎖、M5 的這個系統的板子;
  • the NES-subsystem cases (DMC/OAM/frame-IRQ/PPU registers) — if the new chip lacks that subsystem, simply omit.
  • NES 子系統特定的(DMC/OAM/frameIRQ/PPU 暫存器)—— 新晶片若無對應子系統,直接省略。

In one line: "which six classes of physics to fill with" is the general rule and travels; "which nodes to fill" is this chip's fingerprint and does not.

一句話:「用哪六類物理去補」是通則、帶得走;「補在哪些節點」是這顆晶片的指紋、帶不走。

Honest status誠實狀態 What actually runs today現在真的在跑什麼

One clarification to avoid confusion: these mechanisms are for fidelity, not speed — S1a is ~10% slower than S1 with them armed. The separate question "can this physics accelerate the engine?" is answered elsewhere (short version: no — the giant bidirectional bus SCC is provably un-shatterable by static analysis; see the study and the Robbins-theorem note in the repo).

一個避免混淆的澄清:這些機制是為了忠實度、不是速度 —— arm 起來 S1a 比 S1 慢 ~10%。另一個問題「這些物理能加速引擎嗎?」在別處回答(短版:不能 —— 巨大雙向匯流排 SCC 可證明無法被靜態分析打碎;見 study 與 repo 裡的 Robbins 定理筆記)。