The premise that makes the mapping honest讓對照誠實的大前提
Our resolution model is functionally Bryant's MOSSIM II (1984) minus the X (unknown) state: the priority resolution and the largest-capacitance floating tie-break are his discrete-strength / node-size lattice formalization, inherited via visual6502's chipsim.js. Our "group walk" is what the literature calls channel-connected component (CCC) evaluation. Admitting this first is what makes every claim below meaningful.
我們的解析模型在功能上「就是」Bryant 的 MOSSIM II(1984)去掉 X(未知)態:優先序解析與最大電容浮接保值是他的離散強度 / node-size lattice 形式化,經由 visual6502 的 chipsim.js 繼承。我們的「群組走訪」在文獻裡叫 CCC(channel-connected component)求值。先承認這個,下面的每一條主張才有意義。
Legend for the verdicts below: KNOWN = standard literature, we just cite it · VARIANT = known concept, our form/engineering differs · PLAUSIBLY ORIGINAL = no precedent found by adversarial mapping + title-level search.
判定圖例:已知 = 標準文獻,引用即可 · 變體 = 概念已知,我們的形式/工程不同 · 可能原創 = 對抗式對照 + 標題級搜尋皆未發現先例。
Family 1 — the dynamic fast-path (group-cardinality-specialized resolution)家族 1 —— 動態 fast-path(群組基數特化解析)
| Our technique我們的技術 | Closest prior art最近先行研究 | Verdict + the difference判定 + 差異 |
|---|---|---|
| Static singleton (cls1) — nodes with no pass channels resolve O(1), no walk ever靜態單例(cls1) —— 無 pass 通道的節點永遠 O(1) 解析,免走訪 | MOSSIM II (Bryant 1984), COSMOS (Bryant et al. 1987) | KNOWN已知 — basic static CCC extraction; COSMOS even compiles such nodes into Boolean gates. We just cite it.基本的靜態 CCC 抽取;COSMOS 甚至把這類節點直接編成布林閘。引用即可。 |
| R-1 dynamic singleton (+18.6%) — at the event, if every pass gate is OFF right now, the group is {nn}: O(1) resolve, bit-identical to the walkR-1 動態單例(+18.6%)—— 事件當下若所有通道閘都 OFF,群組就是 {nn}:O(1) 解析,與走訪逐位元相同 | IRSIM (Salz & Horowitz 1989) — dynamic active subnetworks / RC trees over ON switchesIRSIM(Salz & Horowitz 1989)—— 沿 ON 開關的動態 active subnetwork / RC 樹 | VARIANT變體 — the dynamic-sizing concept is IRSIM's; our novelty is implementation-level: a runtime cardinality proof as an early-out dispatch that bypasses the generic relaxation with an O(1) inline path. Frame: "dynamic sizing applied as an early-out execution filter."動態尺寸的概念是 IRSIM 的;我們的新意在實作層:把執行期基數證明當早退派發,以 O(1) 內聯路徑繞過一般化鬆弛。正確的框架:「dynamic sizing 作為 early-out 執行過濾器」。 |
| B1 pair path (+7–9% C# at boost / +14.5% Rust) — prove the group is exactly {seed, neighbour}, resolve the pair inline replicating the walk byte-for-byte (member hash clear, tie-break, write order)B1 成對路徑(C# boost 下 +7~9% / Rust +14.5%)—— 證明群組恰為 {種子, 鄰居},就地解析並逐位元複製走訪語意(成員 hash 清除、tie-break、寫回順序) | COSMOS / Anamos — static template matching (transmission gates, latches) compiled to specialized codeCOSMOS / Anamos —— 靜態樣板匹配(傳輸閘、latch)編成特化程式碼 | VARIANT + a dynamic twist變體 + 動態轉折 — the literature matches subgraphs statically; we do runtime topological pattern matching on the active channel graph. Not theoretically new (it's loop-unrolling the BFS for size = 2), but a highly effective engineering variant — and its payoff profile is a portability datapoint in its own right: +14.5% on the recursive-walk backend (Rust) everywhere, while on the iterative backend (C#) it is operating-point-dependent (+7–9% at boost, under 1% at base clock — it deletes dependent-load chain links, whose wall-clock share grows with frequency).文獻做的是靜態子圖匹配;我們做的是對 active channel graph 的執行期拓撲樣板匹配。理論上不新(= 對 size 2 展開內聯 BFS),但工程上極有效 —— 而它的收益輪廓本身就是移植性數據點:在遞迴走訪後端(Rust)恆為 +14.5%;在迭代後端(C#)隨工作點而變(boost 下 +7~9%、基頻下不到 1% —— 它刪的是相依載入鏈節,佔牆鐘比例隨時脈升高而變大)。 |
Family 2 — the prune family (provably-null event suppression at the source)家族 2 —— 剪枝家族(在源頭壓制可證明無效的事件)
| Our technique我們的技術 | Closest prior art最近先行研究 | Verdict + the difference判定 + 差異 |
|---|---|---|
| P-1 same-state turn-on prune (+11.85%) — equal-state endpoints ⇒ the merge can't change anything, if resolution stays monotone; safety = a load-time structural taint (no-pull-up / ForceCompute components)P-1 同態 turn-on 剪枝(+11.85%)—— 端點同態 ⇒ 合併不會改變任何值,前提是解析走單調路徑;安全性 = 載入期結構 taint(無上拉 / FC 元件) | selective trace / latency (Ulrich 1969); IRSIM's equipotential bypassselective trace / latency(Ulrich 1969);IRSIM 的等電位 bypass | VARIANT變體 — skipping equipotential connections is standard; our contribution is the taxonomy of when an equal-state merge is still unsafe under discrete charge-sharing (the floating tie-break IS the chip's storage) and the structural taint that encodes it. Our first naive version shipped a black screen — that bug is exactly the literature's quirk.跳過等電位連接是標準;我們的貢獻是「同態合併在離散電荷分享下何時仍不安全」的分類學(浮接 tie-break 就是晶片的儲存機制)與將其編碼的結構 taint。我們第一版天真實作直接黑畫面 —— 那個 bug 正是文獻裡的這個陷阱。 |
| P-2 turn-off isolation prune — a statically degree-1, driverless leaf isolates and holds when its only channel opens: suppress the enqueue itselfP-2 關斷隔離剪枝 —— 靜態度 1、無驅動的葉節點,唯一通道斷開必然孤立保值:直接壓制入列 | IRSIM charge-preservation rules (a runtime evaluation outcome)IRSIM 電荷保持規則(執行期求值的結果) | PLAUSIBLY ORIGINAL可能原創 — we elevate the hold-outcome to a load-time static proof and suppress the event before the queue — saving the whole enqueue→pop→resolve chain, not just the propagation. No collision found at title level.我們把保值結果提升為載入期靜態證明,在佇列之前壓制事件 —— 省的是整條 enqueue→pop→resolve 鏈,不只是傳播。標題級搜尋無相撞。 |
| P-3/P-4 capacitance-dominance un-taint (+5.96% / +1.71%) — a driverless node whose capacitance is strictly below ALL channel neighbours can never win the merged group's tie-break ⇒ equal-state merges through it are provable no-opsP-3/P-4 電容支配 un-taint(+5.96% / +1.71%)—— 無驅動節點若電容嚴格小於所有通道鄰居,永遠贏不了合併群組的 tie-break ⇒ 經過它的同態合併可證明為 no-op | Bryant's node-size (κ) lattice (the semantics itself); IRSIM's maxnode size practice (hand-assigned coarse sizes — e.g. precharged buses = size 2, storage = 0 — to simplify resolution); EDA memory extraction (Jou & Jou 1988)Bryant 的 node-size(κ)lattice(語意本體);IRSIM 的 maxnode 尺寸實務(人工指定粗尺寸 —— 如預充匯流排 size 2、儲存 0 —— 以簡化解析);EDA 記憶體抽取(Jou & Jou 1988) |
PLAUSIBLY ORIGINAL — our strongest claim可能原創 —— 最強主張 — using automatically derived dominance inequalities to formally prove tie-break immunity, and spending that proof on event suppression. IRSIM's nearest-neighbour practice is manual coarsening for resolution efficiency — different mechanism, different purpose. The heavy storage cells exclude themselves: having the largest capacitance is what makes them storage.用自動推導的支配不等式形式化證明 tie-break 免疫,並把這個證明花在事件壓制上。IRSIM 那個最近鄰是人工尺寸粗化、目的在解析效率 —— 機制不同、用途不同。重儲存細胞會自己排除自己:電容最大正是它們作為儲存的物理本質。 |
| "Identify memory by its physics, not its name" — pull-up flags + channel-component union-find + capacitance comparisons + driven-pin exclusion ⇒ zero hand-listed nodes, any netlist「用物理認記憶體,不用名字」 —— 上拉旗標 + 通道元件 union-find + 電容比較 + 驅動腳排除 ⇒ 零人工名單、任何網表通用 | EDA state-element extraction (Kam et al. 1995 etc.); Fast-SPICE latency bypass; RTL ODC / clock-gating inferenceEDA 狀態元件抽取(Kam et al. 1995 等);Fast-SPICE latency bypass;RTL ODC / clock-gating 推斷 | KNOWN technique, novel application — presented as methodology, not a claim技術已知、應用新穎 —— 以方法論呈現,不作主張 — extraction is 40-year-old EDA; what's new is spending it on safety classes for event culling. Distinctions: IRSIM/COSMOS extract to know what to evaluate, we extract to know what to drop; Fast-SPICE bypasses numerical integration dynamically, we gate discrete enqueues statically; RTL has explicit DFF primitives, we infer implicit state from a sea of flat transistors.抽取是 40 年老 EDA;新的是把它花在事件剪枝的安全分類上。劃界:IRSIM/COSMOS 抽取是為了知道「該算什麼」,我們是為了知道「該丟什麼」;Fast-SPICE 動態跳過數值積分,我們靜態擋住離散入列;RTL 有顯式 DFF 元件,我們從平坦電晶體海推斷隱式狀態。 |
And the renumbering work (from the earlier consult)還有重編號那一塊(前一次諮詢)
The range-prune + self-captured first-touch key got the same treatment first: its components map to the Inspector-Executor lineage (Saltz 1991; Ding & Kennedy 1999; Strout 2003), trace-driven layout (Chilimbi 2001), deoptimization guards (Hölzle 1992) and ECS archetype sorting — but the synthesis (an in-process, self-contained, event-driven execution-trace capture used to relay out a switch-level simulator's graph memory) has no precedent and was judged a publishable original contribution. The empirically new finding inside it: the locality key's value is the pruned cascade's order, not cache-line density (an equally-dense non-production order measured ±0).
範圍剪枝 + 自我捕捉初次觸碰鍵更早接受了同樣的檢驗:其組件分屬 Inspector-Executor 譜系(Saltz 1991;Ding & Kennedy 1999;Strout 2003)、軌跡導向佈局(Chilimbi 2001)、去優化守衛(Hölzle 1992)與 ECS archetype 排序 —— 但綜合體(同進程、自包含、事件驅動執行軌跡捕捉,用於 switch-level 模擬器的圖記憶體重排)沒有先例,被判定為可發表的原創貢獻。其中實證上新的發現:locality 鍵的價值在已剪枝級聯的順序、而非快取行密度(等密度的非生產順序實測 ±0)。
The honest bottom line誠實的結論
Two top-level original claims — the self-captured trace relayout, and the capacitance-dominance tie-break-immunity proof (P-3/P-4) — plus one secondary claim (P-2's pre-queue static suppression). The dynamic fast-path family (R-1, B1) and P-1 are effective engineering variants of IRSIM/COSMOS-era concepts and are presented as such; the physics-based classification is methodology, not a claim. Title-level scoop scans found no collisions; the one must-cite nearest neighbour (IRSIM's maxnode practice) is distinguished above.
兩個頂層原創主張 —— 自捕捉軌跡重排、電容支配 tie-break 免疫證明(P-3/P-4)—— 加上一個次要主張(P-2 的佇列前靜態壓制)。動態 fast-path 家族(R-1、B1)與 P-1 是 IRSIM/COSMOS 時代概念的高效工程變體,如實呈現;物理分類法是方法論、不是主張。標題級防撞掃描無相撞;唯一必引的最近鄰(IRSIM 的 maxnode 實務)已在上文劃界。
Method note: the mapping comes from adversarial consults with an external model (instructed to refute novelty, not confirm it), cross-checked by title-level searches on IEEE Xplore / ACM DL / Scholar query sets designed to surface a collision if one exists. Full records (claim wordings, search keys, per-item citations) live in the repo under MD/note/2026-06-1*-論文準備*.
方法說明:對照來自對外部模型的對抗式諮詢(指示它反駁原創性、而非確認),再以特意設計來「若有相撞必浮現」的 IEEE Xplore / ACM DL / Scholar 查詢組做標題級交叉驗證。完整記錄(主張措辭、搜尋關鍵字、逐項引用)在 repo 的 MD/note/2026-06-1*-論文準備*。